Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Abstract: A method for forming a trench gate field effect transistor includes forming, in a semiconductor region, a trench followed by forming a dielectric layer lining a sidewall and a bottom surface of the trench. The method also includes, forming a first polysilicon layer on the bottom surface of the trench. The method further includes, forming a conductive material layer on an exposed surface of the first polysilicon layer and forming a second polysilicon layer on an exposed surface of the conductive material layer. The method still further includes, performing rapid thermal processing to cause the first polysilicon layer, the second polysilicon layer and the conductive material layer to react.

Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: Edge termination structures for power semiconductor devices and methods for making such structures are described. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures. Other embodiments are described.

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion, and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material.

Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: A trench gate field effect transistor includes the following steps. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench. A recessed polysilicon layer is formed in the trench. A highly conductive cap layer is formed over and in contact with the recessed polysilicon layer. Rapid thermal processing is performed to cause the recessed polysilicon layer and the highly conductive cap layer to react.

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

Abstract: Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.

Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.

Abstract: A semiconductor structure includes a starting semiconductor substrate having a recessed portion. A semiconductor material is formed in the recessed portion and has a higher resistivity than the starting semiconductor substrate. A body region extends in the semiconductor material, and has a conductivity type opposite that of the semiconductor material. Source regions extend in the body region, and have a conductivity type opposite that of the body region. A gate electrode extends adjacent to but is insulated from the body region. A first interconnect layer extends over and is in contact with a non-recessed portion of the starting semiconductor substrate. The first interconnect layer and the non-recessed portion provide a top-side electrical contact to portions of the starting semiconductor substrate underlying the semiconductor material.

Abstract: A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Abstract: A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess. A vertically conducting device is formed in and over the semiconductor material, where the starting semiconductor substrate serves as a terminal of the vertically conducting device. A non-recessed portion of the starting semiconductor substrate allows a top-side contact to be made to portions of the starting semiconductor substrate extending beneath the semiconductor material.