Abstract: A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess. A vertically conducting device is formed in and over the semiconductor material, where the starting semiconductor substrate serves as a terminal of the vertically conducting device. A non-recessed portion of the starting semiconductor substrate allows a top-side contact to be made to portions of the starting semiconductor substrate extending beneath the semiconductor material.

Abstract: A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

Abstract: Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.