Abstract: A method for identifying apparatuses to be recalled that enables identifying the locations of the products to be recalled, the method including: collecting steps (S2 and S4) of collecting the information items stored in IC tags from the apparatuses with the IC tag via a communication network, a checking step (S6) of checking the information items collected in the collecting step with the information items related to the apparatuses to be recalled, and an identifying step (S8) of identifying the apparatuses to be recalled in the apparatuses with the IC tag based on the checking results.

Abstract: A support pin position determination apparatus (600) that determines the positions at which support pins are to be placed so that the leads of electronic components which have already been mounted on the undersurface of a circuit board are not damaged or the solder lands thereof do not come off includes: a database unit (607); a support pin position determination program storing unit (605); and a calculation control unit (601). The database unit (607) holds component mounting point data (607b), component shape data (607c), and available pin positions at which the support pins are allowed to be placed on a support pin plate (support pin plate data (607a)). The support pin position determination program storing unit (605) stores a support pin position determination program for determining positions at which the support pins are to be placed among the available pin positions, on the basis of the mounting point data and the shape data of the components.

Abstract: The present invention provides a component mounting sequence optimizing method, a component mounting device, a program for executing the component mounting sequence optimizing method, and recording medium in which the program is recorded, in the component mounting device with a component holding head capable of holding a plurality of components and having a component recognition camera. The invention includes a component mounting sequence optimizing device and a mounting sequence for components is determined on basis of a result of comparison between conveyance times for the components and recognition times required for recognitions of the components. Thus cycle time for mounting can be reduced, in comparison with conventional arts, in mounting of components with a component holding head having a plurality of component holding members and having a component recognition camera.

Abstract: A plurality of patterns having the same component placement structure is included in the board, said plurality of patterns corresponding respectively to a plurality of sub-boards obtained by partitioning said board.

Abstract: A component verification method for a mounter (100) that is capable of performing component verification with less labor, is comprised of: a position specification step (S12A) of specifying a placement position in the mounter (100) where a component tape is placed; a read step (S13) of reading component information from an IC tag (426b) that is attached to the component tape or a reel (426); and a verification step (S14) of verifying the component information and the placement position against component arrangement data that indicates components that should be mounted onto the board as well a position where the component tape should be placed.

Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.

Abstract: A method of producing a semiconductor device by dividing a semiconductor wafer into separate pieces of semiconductor chips. This method includes forming a groove with a pattern according to an outer contour of a desired semiconductor chip, holding the semiconductor wafer by a wafer holding mechanism, grinding a back surface of the semiconductor wafer held by the wafer holding mechanism, detecting opening of a bottom face of the groove during the back surface grinding process to determine timing for finishing the back surface grinding. The opening of the groove can be detected by means of a light sensor for detecting light passing through the groove or a microwave sensor for detecting a microwave passing through the groove. In addition, it is possible to suck air inside the groove so as to detect the opening of the groove by a pressure rise in the air inside the groove.

Abstract: A controller optimizes an arrangement of component supply parts installed in a component supply unit while position information of mounting points on a circuit board is taken into account, and then optimizes a mounting path to the circuit board under the arrangement. Since the position information of mounting points is taken into account in obtaining the arrangement of component supply parts, wasteful mounting paths are reduced in comparison with the case of optimizing the mounting path on only the circuit board as in the conventional art, so that the mounting time can be shortened.

Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.

Abstract: An optimizing apparatus (300a) for a mounter equipped with a line gang pickup head which picks up a plurality of components and mounts them on a board comprises: a nozzle set determination unit (305a) for determining a nozzle set which reduces a mounting time in view of the number of times interchanging pickup nozzles and a total task number necessary for mounting the plural components; a nozzle pattern determination unit (305b) for determining an optimal nozzle pattern as well as an arrangement of pickup nozzles (nozzle arrangement) at a nozzle station (119), based on the nozzle set determined by the nozzle set determination unit (305a); and Z-axis arrangement/mounting order optimization unit (305c) for determining an array order of component feeders and a mounting order of components while maintaining the determined nozzle set and nozzle pattern.

Abstract: The following processing is performed when a line gang pickup head can simultaneously pick up a maximum of n (here, 4) components. First, groupings of components of the same type, out of all of the components to be optimized, are set as component tapes and the component tapes are arranged descending order of the number of components to produce a component histogram (406a). Next, a partial histogram (400), which is part of the component histogram (406a), is taken from the component histogram (406a), and is arranged at two-dimensional coordinates where a horizontal axis (the Z-axis) represents an arrangement of component cassettes and a vertical axis represents a number of pickup operations by the line gang pickup head. After this, the component tapes are lined up, by arranging the partial histograms (401a and 401b), so as to produce a diagram (406b) whose width (number of components) in the horizontal axis is n (=4).

Abstract: The following processing is performed when a line gang pickup head can simultaneously pick up a maximum of n (here, 4) components. First, groupings of components of the same type, out of all of the components to be optimized, are set as component tapes and the component tapes are arranged descending order of the number of components to produce a component histogram (406a). Next, a partial histogram (400), which is part of the component histogram (406a), is taken from the component histogram (406a), and is arranged at two-dimensional coordinates where a horizontal axis (the Z-axis) represents an arrangement of component cassettes and a vertical axis represents a number of pickup operations by the line gang pickup head. After this, the component tapes are lined up, by arranging the partial histograms (401a and 401b), so as to produce a diagram (406b) whose width (number of components) in the horizontal axis is n (=4).

Abstract: The present invention provides a component mounting sequence optimizing method, a component mounting device, a program for executing the component mounting sequence optimizing method, and recording medium in which the program is recorded, in the component mounting device with a component holding head capable of holding a plurality of components and having a component recognition camera. The invention includes a component mounting sequence optimizing device (300) and a mounting sequence for components is determined on basis of a result of comparison between conveyance times for the components and recognition times required for recognitions of the components. Thus cycle time for mounting can be reduced, in comparison with conventional arts, in mounting of components with a component holding head having a plurality of component holding members and having a component recognition camera.

Abstract: There are provided a method and device for generating component mounting data in view of productivity, quality assurance, safety, or the like, when components are mounted onto a mounting target, and a component mounting method and device by which a mounting operation can be performed based on the data. Rules that must be observed, or are desired to be observed, based on various conditions such as mounting apparatus and component information and the like are automatically generated in view of productivity, quality assurance, safety, or the like and can be utilized for generation of component mounting data.

Abstract: An optimization apparatus capable of efficiently placing an electronic component. An optimization unit (203) determines a first assignment to the placement apparatus and calculates a first placement time required for placing all the electronic components assigned to the placement apparatus by the first assignment onto a circuit board by the placement apparatus. The optimization unit selects two placement apparatuses among a plurality of placement apparatuses, selects a type of an electronic component assigned for the selected placement apparatus, determines a second assignment by interchanging two selected times assigned, calculates a second placement time required for placing all the electronic components assigned to the placement apparatus by the second assignment onto the circuit board by the placement apparatus, and employs the one of the first assignment and the second assignment which has a smaller placement time.

Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.

Abstract: An electronic component mounting method for placing electronic components successively to component placing positions on a board by component holding devices equipped with a plurality of removable suction nozzles which is operable to hold the electronic components. The method, as an example of its various manners, includes: in placing the electronic components onto a multiple board composed of a plurality of sub-boards, applying a placement step to all the sub-boards, the placement step being a step of placing onto the board all of electronic components that are holdable by an identical suction nozzle; and after completion of the placement step, changing the suction nozzle to another and moving to a next placement step, whereby electronic-component mounting for the individual sub-boards is carried out.

Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.

Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.