Patents by Inventor Ikuo Yoshida

Ikuo Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020072145
    Abstract: In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a theremal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C.
    Type: Application
    Filed: August 3, 2001
    Publication date: June 13, 2002
    Inventors: Naotaka Tanaka, Hideo Miura, Yoshiyuki Kado, Ikuo Yoshida, Takahiro Naito
  • Publication number: 20020013015
    Abstract: Silicon chip having narrow pitches of Au bumps are mounted on a module substrate in such a way that while taking into consideration a difference in coefficient of thermal expansion between the silicon chip and the module substrate, a total pitch of electrode pads of the silicon chip is made narrower than a total pitch of the Au bumps, thereby preventing misregistration between the Au bumps and the electrode pads in the course of heat treatment to ensure reliable contact therebetween.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 31, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiyuki Kado, Tsukio Funaki, Hiroshi Kikuchi, Ikuo Yoshida
  • Publication number: 20010050428
    Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 in face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions for connecting both and relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.
    Type: Application
    Filed: March 8, 2001
    Publication date: December 13, 2001
    Inventors: Hideko Ando, Hiroshi Kikuchi, Ikuo Yoshida, Toshihiko Sato, Tomo Shimizu
  • Publication number: 20010005299
    Abstract: A technique to be applied to improve the reliability of a magnetic disk apparatus is disclosed.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 28, 2001
    Inventors: Yushiyuki Kado, Hiroshi Kikuchi, Ikuo Yoshida
  • Publication number: 20010002163
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: January 26, 2001
    Publication date: May 31, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Publication number: 20010002162
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: January 26, 2001
    Publication date: May 31, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Patent number: 6208525
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: March 27, 2001
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Patent number: 5885852
    Abstract: For manufacturing a packaged semiconductor device, a lead frame with an electrically insulating strip member and a semiconductor chip is placed in a molding unit having upper and lower dies. The upper and lower dies have recessed areas for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies. The lead frame is positioned so that a surface of each lead with the insulating strip member applied thereto is contacted with one of the upper and lower dies having a larger recessed area and a molding line of the molding unit intersects the insulating strip member. The molding unit is closed to clamp the lead frame to depress and thrust into spaces between adjacent leads that part of the strip member which is outside the molding line and to form the cavity of the molding unit.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: March 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Norio Kishikawa, Ikuo Yoshida, Tetsuya Hayashida
  • Patent number: 5305206
    Abstract: An operations manual generation apparatus for use with a host system. The apparatus has an input for receiving ordering input data when an operator places an order following a prescribed procedure for requesting an operations manual from the host system. The apparatus has a first memory which stores first information needed to prepare the requested operations manual. The apparatus also has a second memory for storing instruction information which includes a set of guidance text data which describes the minimum number of operating steps needed to be carried out by an operator. Finally, an edit controller is provided for analyzing the first information to select a suitable combination of guidance text data, so that an operations manual may be output which has been automatically optimized to minimize the number of steps which the operator must take to cause the host system to perform the desired function.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: April 19, 1994
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Inoue, Kanji Kanai, Ikuo Yoshida, Akio Kizawa, Tadaaki Sakashita, Yoshitaka Hori
  • Patent number: 5229447
    Abstract: The present invention provides an alkali soluble pressure sensitive adhesive composition comprising 100 parts by weight of a polymer obtained by polymerization of carboxyl group-containing vinyl monomer as an adhesive component and 50-500 parts by weight of a nonionic surface active agent capable of endowing plasticity as a main additive component.The tack papers or the adhesive tapes using the adhesive compositions according to the invention can be readily dissolved in alkali water in the step of repulping and the reclaimed papers without adhesiveness can be prepared with them.Further, the alkali soluble pressure sensitive adhesive compositions of the present invention are excellent in moisture dependence, tack properties at low temperatures and bleeding properties at high temperatures.
    Type: Grant
    Filed: January 10, 1992
    Date of Patent: July 20, 1993
    Assignee: Saiden Chemical Industry Co., Ltd.
    Inventors: Norihisa Miyajima, Tomohide Fukuzawa, Ikuo Yoshida
  • Patent number: 5188280
    Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: February 23, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5090609
    Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: February 25, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 4945048
    Abstract: A process for producing L-sorbose which comprises culturing a L-sorbose-producing bacterium to obtain a seed culture and subjecting the seed culture to a main fermentation with a batchwise fermentation procedure, wherein a part of said seed culture being subjected to subculture to prepare a seed culture for a next batch, while carrying out the main fermentation with the remainder of said seed culture, and this procedure being repeated, successively. An apparatus for this process is also disclosed.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: July 31, 1990
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Yuji Uchihori, Yasushi Sekitani, Ikuo Yoshida