Patents by Inventor In-kyeong Yoo

In-kyeong Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090285082
    Abstract: An electric field head includes a body portion and a read head having a channel layer provided on an air bearing surface (ABS) of the body portion facing a recording medium and a source and a drain contacting both ends of the channel layer. The electric field head is manufactured by defining a head forming portion of a substrate, separating the head forming portion from the substrate, forming an ABS pattern on a side surface of the separated head forming portion, and forming a channel layer for a read head on a surface of the head forming portion where the ABS pattern is formed. An information storage device includes a ferroelectric recording medium and the electric field head.
    Type: Application
    Filed: October 14, 2008
    Publication date: November 19, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung-soo KO, In-kyeong YOO, Ju-hwan JUNG, Chul-min PARK
  • Patent number: 7602042
    Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a diode structure disposed on the resistor structure, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory devices as described above.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Eon Ahn, In-Kyeong Yoo, Young-Soo Joung, Young-Kwan Cha, Myoung-Jae Lee, David Seo, Sun-Ae Seo
  • Publication number: 20090186444
    Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.
    Type: Application
    Filed: July 10, 2008
    Publication date: July 23, 2009
    Inventors: Choong-Rae Cho, In-Kyeong Yoo, Myoung-Jae Lee
  • Patent number: 7521704
    Abstract: A memory device using a multi-layer with a graded resistance change is provided. The memory device includes: a lower electrode; a data storage layer being located on the lower electrode and having the graded resistance change; and an upper electrode being located on the data storage layer.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-jae Lee, In-kyeong Yoo, Sun-ae Seo, Dong-seok Suh, David Seo, Sang-hun Jeon
  • Publication number: 20090045450
    Abstract: Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body, and a pair of fins protruding from the body; a buried insulating layer filling between the pair of fins; a pair of floating gate electrodes on outer surfaces of the pair of fins to a height greater than that of the pair of fins; and a control gate electrode on the pair of floating gate electrodes.
    Type: Application
    Filed: October 23, 2007
    Publication date: February 19, 2009
    Inventors: June-mo Koo, Suk-pil Kim, Young-gu Jin, Won-joo Kim, In-kyeong Yoo, Yoon-dong Park
  • Patent number: 7482648
    Abstract: In an electronic device, and a method of manufacturing the same, the electronic device includes a first substrate, a first lower capacitor on the first substrate, a first lower switching element on the first lower capacitor, and a second substrate on the first lower switching element. The electronic device may further include a second lower switching element which is isolated from the first lower capacitor, and an upper capacitor on the second substrate, the lower electrode of the upper capacitor being connected to the second lower switching element.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Takashi Noguchi, In-kyeong Yoo, Young-soo Park
  • Patent number: 7479212
    Abstract: A high-density data storage medium, a method of manufacturing the data storage medium, a high-density data storage apparatus, and methods of writing data on, and reading and erasing data from the data storage medium by using the data storage apparatus are provided. The data storage medium includes a lower electrode, an insulation layer deposited on the lower electrode, a photoelectron emission layer deposited on the insulation layer and having a plurality of protrusions from which photoelectrons are emitted due to collisions between the protrusions and photons, and a dielectric layer deposited on the photoelectron emission layer and storing the photoelectrons emitted from the photoelectron emission layer.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-bum Hong, In-kyeong Yoo, Ju-hwan Jung
  • Publication number: 20080316807
    Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 25, 2008
    Inventors: Jae-Woong Hyun, In-Kyeong Yoo, Yoon-Dong Park, Choong-Rae Cho, Sung-II Cho
  • Publication number: 20080315285
    Abstract: Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode.
    Type: Application
    Filed: February 21, 2008
    Publication date: December 25, 2008
    Inventors: Tae-hee Lee, Jae-woong Hyun, Ju-hee Park, In-kyeong Yoo, Yoon-dong Park, Won-joo Kim, Jung-hoon Lee
  • Publication number: 20080257861
    Abstract: A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.
    Type: Application
    Filed: July 30, 2007
    Publication date: October 23, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Soo-hwan Jeong, Sun-ae Seo, In-sook Kim
  • Patent number: 7439566
    Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jae-Woong Hyun, In-Kyeong Yoo, Yoon-Dong Park, Choong-Rae Cho, Sung-Il Cho
  • Patent number: 7417271
    Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Stefanovich Genrikh, Choong-rae Cho, In-kyeong Yoo, Eun-hong Lee, Sung-Il Cho, Chang-wook Moon
  • Patent number: 7414295
    Abstract: A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a second conductive layer which are sequentially stacked on the first conductive layer, a first current direction limiting unit and a second current direction limiting unit formed on the second conductive layer by being separated within a space, a third conductive layer and a fourth conductive layer formed on the first current direction limiting unit and the second current direction limiting unit, respectively, a word line connected to the third conductive layer, a bit line connected to the fourth conductive layer, and a voltage lowering unit connected to the word line.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Rae Cho, In-Kyeong Yoo, Myoung-Jae Lee
  • Patent number: 7407856
    Abstract: A method of manufacturing a memory device includes defining a field region and an active region in a substrate, forming a field oxide layer on the field region, forming an insulating layer on the active region, patterning the insulating layer to form first and second bit lines separated from and parallel to each other on the active region, forming a memory element for storing data in a nonvolatile state, wherein the memory element passes across the first and second bit lines, and forming a word line on the insulating layer and the memory element.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: August 5, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Byong-man Kim
  • Patent number: 7400027
    Abstract: A nonvolatile memory device having two or more resistors and methods of forming and using the same. A nonvolatile memory device having two resistance layers, and more particularly, to a nonvolatile memory device formed and operated using a resistance layer having memory switching characteristics and a resistance layer having threshold switching characteristics. The nonvolatile semiconductor memory device may include a lower electrode; a first resistance layer having at least two resistance characteristics formed on the lower electrode, a second resistance layer having threshold switching characteristics formed on the first resistance layer, and an upper electrode formed on the second resistance layer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics, Co., LTD
    Inventors: Young-Soo Joung, Yoon-Dong Park, In-Kyeong Yoo, Myoung-Jae Lee, Sun-Ae Seo, Hye-Young Kim, Seung-Eon Ahn, David Seo
  • Publication number: 20080138659
    Abstract: Example embodiments may provide data storage devices using movement of a magnetic domain wall and/or a method of operating magnetic domain data storage devices. The data storage device may include a first magnetic layer for writing data having two magnetic domains magnetized in different directions, a second magnetic layer for storing data at a side of the first magnetic layer, a data recording device connected to the first magnetic layer and the second magnetic layer, and a plurality of reading heads configured to read the second magnetic layer. The data storage device may store a larger amount of data without requiring moving mechanical systems.
    Type: Application
    Filed: October 31, 2007
    Publication date: June 12, 2008
    Inventors: Chee-kheng Lim, In-kyeong Yoo, Sung-hoon Choa
  • Publication number: 20080121865
    Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 29, 2008
    Inventors: Seung-Eon Ahn, In-Kyeong Yoo, Young-Soo Joung, Young-Kwan Cha, Myoung-Jae Lee, David Seo, Sun-Ae Seo
  • Patent number: 7378328
    Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: May 27, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-bong Choi, In-kyeong Yoo, Jae-uk Chu
  • Patent number: 7355951
    Abstract: A rapid data recording/reproducing method, a data recording system adopting the same, media for the system, and a tracking method, wherein the recording/reproducing method includes preparing media having a data recording layer in which a phase change is generated through electron absorption, generating electrons using an electron generating source at a position separated from the data recording layer by a predetermined interval, forming a magnetic field on the path of the electrons and cyclotron moving the electrons, recording data through local melting and cooling due to absorption of the electrons by the data recording layer. A micro-tip does not contact the data recording layer during electron collisions therewith, hence no damage is caused by or to the micro-tip. The present invention allows the region where the electron beam reaches the data recording layer to be minimized thereby maximizing the data recording density.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: April 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-kyeong Yoo, Won-bong Choi, Hyun-jung Shin
  • Publication number: 20070278425
    Abstract: An emitter for an electron-beam projection lithography system includes a photoconductor substrate, an insulating layer formed on a front surface of the photoconductor substrate, a gate electrode layer formed on the insulating layer, and a base electrode layer formed on a rear surface of the photoconductor substrate and formed of a transparent conductive material. In operation of the emitter, a voltage is applied between the base electrode and the gate electrode layer, light is projected onto a portion of the photoconductor substrate to convert the portion of the photoconductor substrate into a conductor such that electrons are emitted only from the partial portion where the light is projected. Since the emitter can partially emit electrons, partial correcting, patterning or repairing of a subject electron-resist can be realized.
    Type: Application
    Filed: August 7, 2007
    Publication date: December 6, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: In-kyeong Yoo, Chang-wook Moon, Chang-hoon Choi