Abstract: According to an aspect of the present disclosure, a capacitor component includes a body including a dielectric layer and an internal electrode layer; and an external electrode disposed on the body and connected to the internal electrode layer, wherein the body further includes a withstand voltage layer disposed in a region spaced apart by more than 0 to 30 nm or less in a direction from a boundary of the internal electrode layer toward the dielectric layer, and having ionic mobility, lower than ionic mobility of the dielectric layer.

Abstract: A data loading and processing system, and a method therefor are disclosed. In the present invention, a collection server confirms the state of target resources before collecting data, determines a data collecting and loading method for the corresponding resources on the basis of the confirmed state of the resources, transmits a data collection request to a data server, collects the data from the data server through the determined data collecting and loading method, and loads the collected data in a big data platform so as to collect and load data by an optimum data collecting and loading method according to the current state of objects to be collected and objects to be loaded, and thus can increase overall system operation efficiency.

Abstract: In one example, an electronic device comprises a substrate having a top side and a bottom side, an electronic component over the top side of the substrate, and an encapsulant over the top side of the substrate. The substrate comprises a dielectric structure comprising a first dielectric layer and a conductive structure in the dielectric structure and comprising a first conductor tier in the first dielectric layer comprising a first trace exposed from a top side of the first dielectric layer and partially extending through the first dielectric layer and a first via exposed from the top side of the first dielectric layer and a bottom side of the first dielectric layer and extending from the top side of the first dielectric layer to the bottom side of the first dielectric layer. The first trace and the first via have non-stepped sidewalls extending vertically. Other examples are also disclosed herein.

Abstract: A method of providing a secure communication service using a secure communication device equipped with a quantum-random-number-based encryption chip. The method includes: in response to a first user terminal executing a secure communication device service app for secure communication and inputting a personal information number (PIN) or pattern, performing device authentication between a first user secure communication device and the first user terminal and then performing remote authentication between the first user terminal and a management server; in response to user authentication being completed, generating a quantum secret key a by a quantum encryption chip of the first user secure communication device and transmitting a quantum public key A to a second user secure communication device; and creating, by the first user secure communication device, a speech secure communication channel for communication with the second user secure communication device by inducing and storing the quantum encryption key.

Abstract: A method for managing an application executed in a user terminal according to an embodiment of this disclosure includes executing a launcher application on the user terminal, displaying a first application list within a first GUI of the launcher application, installing, in the user terminal, a first application selected by a user from applications included on the first application list, displaying a second application list within a second GUI of the launcher application and executing a second application selected by the user from applications included on the second application list.

Abstract: A random number generator resistant to side-channel attacks. The random number generator includes an entropy unit generating random pulses, a random frequency clock generator generating random frequencies by receiving random pulses output from the entropy unit, and an MCU externally masking a specific operation or a specific instruction based on a random frequency received from the random frequency clock generator.

Abstract: In one example, an electronic device, comprises a substrate, comprising a first dielectric having a top surface and a bottom surface, and a first conductor in the first dielectric and comprising a first via and a first trace over the first via. The first trace comprises a first trace sidewall and a first trace base, and the first via comprises a first via sidewall. The first conductor comprises a first arcuate vertex between the first trace sidewall and the first trace base, and a second arcuate vertex between the first via sidewall and the first trace base, an electronic component over the top surface of the substrate, and an encapsulant over the top surface of the substrate and contacting a lateral side of the electronic component. Other examples and related methods are also disclosed herein.

Abstract: A method and a system of providing a quantum random number based on a quantum entropy source. The method includes generating a quantum random number and providing the quantum random number to a device. The generating of the quantum random number based on the quantum entropy source includes determining, by a management unit, whether quantum random numbers stored in a storage are insufficient; generating a quantum random number based on the quantum entropy source using a quantum random number generator provided in a production unit in response to a determination that the quantum random numbers are insufficient; verifying, by a verification unit, the generated quantum random number based on NIST SP800-90B and SP800-22; and in response to quality of the generated quantum number satisfying a criterion, storing the verified quantum random number in the storage.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer having a main component represented by (Ba1-xCax) (Ti1-y(Zr, Hf)y)O3 (where, 0?x?1, 0?y?0.5), and including first and second internal electrodes alternately stacked with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein at least one of the dielectric layer and the internal electrode includes Sn or Dy. If Sn, an average content of Sn at an interface between the dielectric layer and the internal electrode is within a range of 5 at % or more and 20 at % or less. If Dy, an average content of Dy at an interface between the dielectric layer and the internal electrode is within a range of 1 at % or more and 5 at % or less.

Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes laminated with the dielectric layers interposed therebetween, and an external electrode disposed externally on the body and connected to one or more of the plurality of internal electrodes. One of the plurality of dielectric layers includes a barium titanate composition including a Sn component. One of the plurality of internal electrodes includes a Sn component. The one of the plurality of dielectric layers has a Sn content equal to at least twice a Sn content of the one of the plurality of internal electrodes adjacent to the one of the plurality of dielectric layers.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer, a plurality of first and second internal electrodes disposed inside the ceramic body, exposed to the first and second surfaces, and having ends exposed to the third or fourth surface, and a first side margin portion and a second side margin portion disposed on side portions of the plurality of first and second internal electrodes exposed to the first and second surfaces. A ratio Db/Da satisfies 1.00 to 1.07, inclusive, where ‘Db’ is a distance, in a stacking direction of the dielectric layer, between both end points of respective edge regions of the first side margin portion and the second side margin portion, and ‘Da’ is a distance in a central region of the ceramic body in the stacking direction.

Abstract: A ceramic electronic component includes: a body including dielectric layers and internal electrodes; and external electrodes disposed on the body and connected to the internal electrodes, wherein the dielectric layer includes a plurality of dielectric crystal grains, and at least one of the plurality of dielectric crystal grains has a core-double shell structure, the double shell includes a first shell surrounding at least a portion of the core and a second shell surrounding at least a portion of the first shell, the first shell includes a first element, one or more of Sn, Sb, Ge, Si, Ga, In, or Zr, and the second shell includes a second element, one or more of Ca or Sr.

Abstract: A multilayer capacitor includes a capacitor body including an active region having dielectric layers and internal electrodes alternately stacked therein, the capacitor body including upper and lower covers disposed on upper and lower surfaces of the active region, respectively; and an external electrode disposed on an external surface of the capacitor body. In one of the upper and lower covers, a portion thereof between a boundary surface of the active region and a boundary surface of the capacitor body is divided into a first cover region adjacent to the active region and a second cover region adjacent to the boundary surface of the capacitor body, and the first cover region includes grains having a core-shell structure doped with Sn. The first cover region includes 20% or more of Sn-doped core-shell structure grains, compared to the total of grains in the first cover region.

Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers, and a plurality of internal electrodes stacked with one of the dielectric layers interposed therebetween, and external electrodes disposed on external surfaces of the body and connected to the internal electrodes, respectively. The plurality of dielectric layers include a dielectric expressed by empirical formula BaM1aTi1-xSnxM2bO3 (0.008?x?0.05, 0.006?a?0.03, and 0.0006?b ?0.006) in which M1 includes a rare earth element, and M2 includes at least one of Mn or V.

Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.

Abstract: An edge computing method for flexibly allocating a computing resource includes receiving an edge module and a container resource allocation value, generating a container based on the container resource allocation value and arranging the edge module in the generated container. The edge module is distributed to an edge computing device to perform a predetermined data processing. The container is a software component of the edge computing device providing an isolated computing environment for driving the edge module. The edge computing device is installed on-premise. The edge computing device can flexibly adjust available computing resources according to the current working situation and a resource requirement. In response to an environment, in which data traffic is flexible according to time or situation, such as a manufacturing plant, allocated resources of the edge computing device can be quickly adjusted, thereby a stable service can be provided.

Abstract: An edge computing device controlling method includes executing some function modules of a plurality of function modules for processing a service request from a user device on a first edge computing device of a plurality of edge computing devices and additionally executing the some function modules on a second edge computing device of the plurality of edge computing devices when additional resource is required for the some function modules.

Abstract: In one example, a semiconductor device, comprising a substrate having a top side and a bottom side, an electronic device on the top side of the substrate, a first encapsulant on the top side of the substrate contacting a side of the electronic device, a second encapsulant on the bottom side of the substrate, wherein the second encapsulant includes an undercut at an end of the second encapsulant, and a cover layer comprising a top cover on a top side of the first encapsulant and a side cover on a side of the first encapsulant and a side of the substrate, wherein the side cover extends adjacent to the undercut. Other examples and related methods are also disclosed herein.

Abstract: An Fe-based nanocrystalline alloy is represented by Composition Formula, (Fe(1-a)M1a)100-b-c-d-e-gM2bBcPdCueM3g, where M1 is at least one element selected from Co and Ni, M2 is at least one element selected from the group consisting of Nb, Mo, Zr, Ta, W, Hf, Ti, V, Cr, and Mn, M3 is at least one element selected from the group consisting of C, Si, Al, Ga, and Ge, and 0?a?0.5, 2?b?3, 9?c?11, 1?d?2, 0.6?e?1.5, and 9?g?11.

Abstract: Disclosed herein are a transformer and a method of manufacturing the same. The transformer includes: a primary side winding having a loop shape; a secondary side winding formed on the same plane as that of the primary side winding in a remaining section except for at least a section at which it intersects with the primary side winding and having the same loop shape as that of the primary side winding so as to be electromagnetically coupled to the primary side winding; and an intersecting section formed so that the primary side and secondary side windings having the sum of the turn numbers of 3 or more intersect with each other in a two-layer structure, wherein the intersecting section includes at least one point of intermediate node having one side connected in a first layer and the other side connected in a second layer.