Patents by Inventor In-Young Chang

In-Young Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153073
    Abstract: A method for training an artificial neural network for detecting a prostate cancer from a TURP pathological image, includes: acquires a plurality of acquiring pathological images for primary training, each being a prostate needle biopsy pathological image or a radical prostatectomy pathological image; using the pathological images to primarily train an artificial neural network for determining prostate cancer; acquiring TURP pathological images; and using the TURP pathological images to secondarily train the primarily trained artificial neural network, wherein each TURP pathological image includes a non-prostate tissue region and/or a cauterized prostate tissue region, and does not include any prostate cancer lesion region.
    Type: Application
    Filed: March 7, 2022
    Publication date: May 9, 2024
    Inventors: Joon Young CHO, Hye yoon CHANG, Tae Yeong Kwak, Sun woo KIM
  • Publication number: 20240153655
    Abstract: According to an embodiment of the present invention, an emergency core cooling system (ECCS) valve provided between a reactor vessel of a system-integrated modular advanced reactor (SMART) and a small containment vessel formed to surround the reactor vessel so that a coolant is filled in a space between the reactor vessel and the small containment vessel in the event of a loss of coolant accident (LOCA) includes an outer shell connected to the reactor vessel and formed to protrude toward the small containment vessel and having a connector formed therein so as to communicatively connect an inside of the reactor vessel to an inside of the small containment vessel, an inner shell provided inside the outer shell at a preset distance from an inner wall of the outer shell, a piston movably constrained and inserted through a piston opening formed in the inner shell at a position facing the connector of the outer shell to open and close the connector, and a spring provided on an outer circumferential surface of the p
    Type: Application
    Filed: November 1, 2021
    Publication date: May 9, 2024
    Inventors: Soo Jai SHIN, Cheongbong CHANG, Seungyeob RYU, Han-Ok KANG, Young-In KIM, Ji Han CHUN, Sung Won LIM, Joo Hyung MOON, Hun Sik HAN, Seok KIM, Hyunjun CHO
  • Publication number: 20240149752
    Abstract: An embodiment relaxation seat for a vehicle includes a seat cushion lower frame configured to be mounted on a seat rail, a seat cushion upper frame connected to the seat cushion lower frame in a tilting-enabled manner, a seat back frame connected to the seat cushion upper frame, a locking device mounted at a predetermined position on the seat cushion upper frame, a front link hinge-connecting between the seat cushion upper frame and a front end portion of the seat cushion lower frame, a rear link hinge-connecting between the seat cushion upper frame and a rear end portion of the seat cushion lower frame, and a support bar connecting between the locking device and the front link in a manner that is movable backward and forward and configured to support the front link for rotation or fixation thereof.
    Type: Application
    Filed: April 17, 2023
    Publication date: May 9, 2024
    Inventors: Byeong Kwang Kim, Young Bok Sung, Yong Chang Jung, Young Jun Kim
  • Patent number: 11980037
    Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
  • Publication number: 20240145752
    Abstract: A fuel cell apparatus of the disclosure includes a case having defined therein a first accommodation space and a second accommodation space, which are isolated from each other by a partition wall, a first cover covering the first accommodation space in the case, a second cover covering the second accommodation space in the case, a power distribution unit disposed in the first accommodation space, and a power conversion unit disposed in the second accommodation space.
    Type: Application
    Filed: May 11, 2023
    Publication date: May 2, 2024
    Inventors: Sae Kwon CHANG, Jong Jun LEE, Woo Young LEE, Yoon Tae KIM
  • Publication number: 20240143173
    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Mu-Tien CHANG, Dimin NIU, Hongzhong ZHENG, Sun Young LIM, Indong KIM, Jangseok CHOI
  • Patent number: 11969213
    Abstract: Provided are apparatuses, a non-transitory computer-readable medium or media, and methods for supporting predicting of vascular disease using a fundus image of a subject. In certain aspects, disclosed a method including the steps of: extracting a feature information from a first fundus image of the subject based on a machine learning model; generating a second fundus image having a feature which is corresponding to the feature information by mapping a saliency factor to the first fundus image; and displaying the first fundus image and the second fundus image on a display device.
    Type: Grant
    Filed: May 9, 2021
    Date of Patent: April 30, 2024
    Assignee: XAIMED CO., LTD.
    Inventors: Sang Min Park, Joo Young Chang, Choong Hee Lee, Il Hyung Shin
  • Patent number: 11973584
    Abstract: This application relates to a noise signal generating apparatus. In one aspect, the apparatus includes a bandwidth expansion unit configured to generate a noise signal having a second bandwidth by expanding a noise source signal having a first bandwidth to the second bandwidth that is greater than the first bandwidth. The apparatus may also include a randomization unit configured to perform randomization and output the generated noise signal having the second bandwidth.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Agency for Defense Development
    Inventors: Jaewon Chang, Jeong Ho Ryu, Joo Rae Park, Young Ju Park, Byeong Nam Lee
  • Publication number: 20240136244
    Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Je-Young Chang, Ram Viswanath, Elah Bozorg-Grayeli, Ahmad Al Mohammad
  • Publication number: 20240130207
    Abstract: A display device includes a display panel, a filler layer, a reflection control layer, a plurality of light-blocking patterns, and an encapsulation substrate. The low reflection layer is disposed on the display panel. The filler layer is disposed on the display panel. The reflection control layer includes a first catalyst and is disposed on the filler layer. The plurality of light-blocking patterns is disposed between the filler layer and the reflection control layer. The encapsulation substrate is disposed on the reflection control layer.
    Type: Application
    Filed: May 1, 2023
    Publication date: April 18, 2024
    Inventors: HYEBEOM SHIN, DAEWON KIM, SU JEONG KIM, JONGHO SON, KYUNGHEE LEE, JINHYEONG LEE, SUN-YOUNG CHANG
  • Publication number: 20240128274
    Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 18, 2024
    Inventors: Vasudha Gupta, Jae Won Choi, Shih Chang Chang, Tsung-Ting Tsai, Young Bae Park
  • Publication number: 20240128494
    Abstract: A pouch type all-solid-state battery including a reference electrode is disclosed. In the all-solid-state battery, a potential variation of each electrode is accurately measured because the ion transfer path between the reference electrode and a positive electrode/negative electrode is short. Accordingly, the all-solid-state battery secures a desired cell performance while having battery specifications similar to actual battery specifications.
    Type: Application
    Filed: September 5, 2023
    Publication date: April 18, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Jae Ho Shin, Ji Chang Kim, Hyun Min Seo, Young Jin Nam, Ga Young Choi
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240119064
    Abstract: Disclosed herein is an apparatus and method for synchronizing a block in a blockchain network. The apparatus synchronizes node information of existing participating nodes connected to a blockchain network by joining the blockchain network, determines synchronization target blocks by calculating the current section of a blockchain using an agreed-upon block received from the existing participating nodes, receives a block header of each section and the segment hash table of a snapshot that are verification data for verifying synchronization target data for the synchronization target blocks from participating nodes that are not connected as peers, among the existing participating nodes, generates a snapshot by receiving snapshot segments and the blocks of the current section, which are the synchronization target data, from participating nodes connected as peers, among the existing participating nodes, verifies the snapshot generated from the snapshot segments, and synchronizes the verified snapshot.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 11, 2024
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-Chang KIM, Jong-Choul YIM, Jin-Tae OH, Chang-Hyun LEE
  • Publication number: 20240121122
    Abstract: Disclosed are an apparatus and method for electing a committee node in a blockchain. The apparatus for electing a committee node in a blockchain is configured to transmit a staking transaction including validator information to a blockchain system to register a validator node, generate a draw pool for electing a committee node based on the validator information, change entries of the draw pool using a predefined shuffling algorithm, select a preset number of top entries as votes of a committee member from among the entries of the shuffled draw pool, and elect, as the committee node, the validator node that has acquired votes of a committee.
    Type: Application
    Filed: August 23, 2023
    Publication date: April 11, 2024
    Inventors: Jong-Choul YIM, Jin-Tae OH, Young-Chang KIM, Chang-Hyun LEE
  • Patent number: 11955076
    Abstract: An example method includes estimating, based on content to be displayed at a display of a mobile computing device at a future time, an amount of power to be used by the display at the future time; selecting, based on the estimated power level, a power converter of a plurality of power converters of the mobile computing device, each of the plurality of power converters optimized for a different output power range; and causing electrical power from the selected power converter to be supplied to the display at the future time.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Ji Hoon Lee, Sun-il Chang, Sang Young Youn
  • Patent number: 11954891
    Abstract: Provided is a method of compressing an occupancy map of a three-dimensional (3D) point cloud, and more specifically, a method of compressing an occupancy map of a point cloud in which an occupancy map image of a point cloud existing in a 3D space is compressed based on a compression quality or a patch-by-patch inspection method of the occupancy map image so that compression distortion is minimized when reconstructing the compressed occupancy map image so as to remarkably improve the quality of a reconstructed occupancy map image.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 9, 2024
    Assignees: Electronics and Telecommunications Research Institute, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Eun Young Chang, Euee Seon Jang, Tian Yu Dong, Ji Hun Cha, Kyu Tae Kim, Jae Young Ahn
  • Publication number: 20240111785
    Abstract: Disclosed herein is a method for adding an additional chain to a blockchain. The method includes depositing, by a node of the blockchain, an asset corresponding to the additional chain; selecting the node as one of consensus nodes for connecting an additional block to the additional chain based on a share value corresponding to the asset; and performing, by the node, distributed consensus for connecting the additional block. Here, nodes constituting the blockchain include major shareholder nodes for processing transactions.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 4, 2024
    Inventors: Jin-Tae OH, Young-Chang KIM, Chang-Hyun LEE, Jong-Choul YIM
  • Publication number: 20240114163
    Abstract: Disclosed is an encoder which receives first to third input frames included first intra period and outputs a bitstream corresponding to the third input frame. The encoder includes a motion compensation unit that generates a first reference frame corresponding to the first input frame and a second reference frame corresponding to the second input frame, a union operation unit that generates an overlap frame by performing a union operation based on the first reference frame and the second reference frame, and an inter prediction unit that generates an occupancy code by performing an inter prediction operation on the overlap frame and the third input frame. In this case, the bitstream includes the occupancy code.
    Type: Application
    Filed: September 15, 2023
    Publication date: April 4, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Eun Young CHANG, Euee S JANG, Xin LI, Jihun CHA, Tianyu DONG, Jae Young AHN
  • Patent number: 11948520
    Abstract: PWM-frame rate misalignment is mitigated through implementation of a discrete variable refresh rate (VRR) scheme. A target frame rate is limited to a frame rate selected from only those frame rates that facilitate alignment of each frame period to a specified edge of a PWM cycle of a brightness control signal of a display panel. This alignment results in each frame period at the selected frame rate starting at a same point in a corresponding PWM cycle and ending at a same point in a corresponding PWM cycle to help ensure a constant effective duty cycle across each successive frame period, which in turn mitigates perception of flicker that otherwise would arise. Further, the discrete VRR scheme can employ a compensation mode for compensating for the delay in rendering or otherwise obtaining a frame for display so as to maintain a consistent duty cycle in the brightness control signal.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 2, 2024
    Assignee: GOOGLE LLC
    Inventors: Sang Young Youn, Sun-il Chang, Wonjae Choi, Sangmoo Choi