Patents by Inventor Ioannis Koltsidas

Ioannis Koltsidas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391877
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request at a storage system which includes more than one storage device, determining a storage location for data included in the write request, and determining a storage location for parity information corresponding to the data included in the write request. A first copy of the data included in the write request is sent to a first storage device which corresponds to the storage location for the data included in the write request. Moreover, a second copy of the data included in the write request is sent to a second storage device which corresponds to the storage location for the parity information. One or more instructions to compute the parity information via a decentralized communication link with the remaining storage devices are sent to the second storage device. The first storage device is different than the second storage device.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Radu I. Stoica, Roman A. Pletka, Ioannis Koltsidas, Nikolas Ioannou, Antonios K. Kourtis, Sasa Tomic, Charalampos Pozidis, Brent W. Yardley
  • Patent number: 10503590
    Abstract: The invention relates to a storage system comprising one or more storage controllers, two or more storage devices and two or more storage clients, the storage controllers, the storage devices and the storage clients being coupled via a network in order to exchange information between the storage controllers, said storage devices and said storage clients, wherein each storage client is adapted to provide data-path-storage commands to the storage devices via the network bypassing the storage controllers, wherein the storage system is adapted to provide data redundancy using a data redundancy scheme higher than RAID 1.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ioannis Koltsidas, Nikolas Ioannou, Robert Haas, Charalampos Pozidis, Thomas D. Weigold, Thomas P. Parnell
  • Publication number: 20190361771
    Abstract: A computer-implemented method, according to one embodiment, includes: sequentially adding metadata information that has been extracted from a received write command to a metadata buffer, and adding parity information that has been extracted from the received write command to a parity buffer. The data corresponding to the received write command is also sent to memory. A determination is made as to whether an open segment in the memory which corresponds to the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. Moreover, the metadata information is destaged from the metadata buffer and parity information is destaged from the parity buffer to a physical storage location in the memory.
    Type: Application
    Filed: July 10, 2019
    Publication date: November 28, 2019
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Publication number: 20190361772
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving, at a storage drive, a portion of a write command. Metadata information is extracted from the received portion of the write command, and sequentially added to a metadata buffer. Parity information is extracted from the received portion of the write command, and adding to a parity buffer. The data in the received portion of the write command is stored in a memory in the storage drive. A determination is also made as to whether an open segment in the memory which corresponds to the received portion of the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. The metadata information and parity information is also destaged from the respective buffers to a physical storage location in the memory.
    Type: Application
    Filed: July 10, 2019
    Publication date: November 28, 2019
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Patent number: 10482032
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Publication number: 20190310915
    Abstract: Embodiments for optimizing resource consumption through partial parity information eviction in a storage system of a data storage environment. One or more cooperative Redundant Array of Independent Disks (RAID) parity computations are performed by evicting partial parity data from a RAID controller memory to a storage entity prior to a full stripes worth of data being monotonically written to the storage entity. The storage entity assembles the partial parity data from the one or more cooperative RAID parity computations into a single parity computation valid for the full stripes worth of data, thereby offloading parity computation to the storage entity to more efficiently utilize the RAID controller memory resources.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles CAMP, Ioannis KOLTSIDAS, Christopher DENNETT, Andrew D. WALLS
  • Patent number: 10437670
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write command to write data, the write command being received from a log structure array at a host location. The computer-implemented method also includes: extracting metadata information from the received write command; sequentially adding the extracted metadata information to a metadata buffer; extracting parity information from the received write command; adding the extracted parity information to a parity buffer; sending the data corresponding to the received write command to memory; determining whether an open segment in the memory which corresponds to the write command has been filled; updating the parity buffer with the metadata information included in the metadata buffer in response to determining that the open segment has been filled; and destaging the metadata information from the metadata buffer and parity information from the parity buffer to a physical storage location in the memory.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Publication number: 20190272232
    Abstract: A computer-implemented method, according to one embodiment, includes: retrieving a physical block address corresponding to a logic block address, extracting information from the physical block address, and performing a lookup operation in cache using the extracted information. A range check of the physical block address is further performed in response to the lookup operation succeeding, while data is read from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, as well as parallel writes to different non-volatile memory channels. The cache architecture further supports pipelining of the parallel writes to different non-volatile memory planes. Moreover, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic, Andrew D. Walls
  • Patent number: 10387317
    Abstract: A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to: retrieve a physical block address corresponding to a logic block address; extract information from the physical block address; perform a lookup operation in cache using the extracted information; perform a range check of the physical block address in response to the lookup operation succeeding; and read data from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, in addition to supporting parallel writes to different non-volatile memory channels. The cache architecture also supports pipelining of the parallel writes to different non-volatile memory planes. The non-volatile memory controller is also configured to perform a direct memory lookup in the cache based on a physical block address.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic, Andrew D. Walls
  • Publication number: 20190213124
    Abstract: An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Sasa Tomic
  • Publication number: 20190212949
    Abstract: A technique for operating a data storage system includes receiving uncompressed data. The uncompressed data is organized into data strips of a stripe. The data strips are compressed subsequent to the organizing. Parity information for the compressed data strips is calculated. Storage of the compressed data strips and the parity information for the stripe is initiated on respective storage devices of the data storage system.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: ROMAN A. PLETKA, RADU I. STOICA, IOANNIS KOLTSIDAS, NIKOLAS IOANNOU, SASA TOMIC, ANTONIOS K. KOURTIS, CHARALAMPOS POZIDIS
  • Patent number: 10339048
    Abstract: An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic
  • Publication number: 20190163592
    Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: CHARLES J. CAMP, IOANNIS KOLTSIDAS, ROMAN A. PLETKA, ANDREW D. WALLS
  • Publication number: 20190163764
    Abstract: Techniques for selecting a storage node of a storage system to store data include applying a first function to at least some data chunks of an extent to provide respective first values for each of the at least some data chunks. A storage node, included within multiple storage nodes of a storage system, is selected to store the extent based on a majority vote derived from the respective first values.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: NIKOLAS IOANNOU, IOANNIS KOLTSIDAS, ROMAN A. PLETKA, CHENG-CHUNG SONG, RADU STOICA, SASA TOMIC, ANDREW D. WALLS
  • Publication number: 20190146671
    Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Publication number: 20190138211
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include identifying, in a storage system including multiple storage devices having respective sets of storage regions, respective default low storage region thresholds that are used for garbage collection. For each given storage region, a time threshold and an alternative low storage region threshold greater than the default low storage region threshold for the given storage device are defined. While processing input/output operations for each given storage device, a count of unused storage regions in the given storage device is maintained, a timer is initialized, and upon the timer matching the time threshold for the given storage device, a garbage collection operation is initiated. In some embodiments, processing the input/output operations includes using a log-structured array format.
    Type: Application
    Filed: September 20, 2018
    Publication date: May 9, 2019
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nikolas IOANNOU, Ioannis KOLTSIDAS, Amit MARGALIT, Rivka MATOSEVICH
  • Publication number: 20190087268
    Abstract: The invention relates to a storage system comprising one or more storage controllers, two or more storage devices and two or more storage clients, the storage controllers, the storage devices and the storage clients being coupled via a network in order to exchange information between the storage controllers, said storage devices and said storage clients, wherein each storage client is adapted to provide data-path-storage commands to the storage devices via the network bypassing the storage controllers, wherein the storage system is adapted to provide data redundancy using a data redundancy scheme higher than RAID 1.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: Ioannis Koltsidas, Nikolas Ioannou, Robert Haas, Charalampos Pozidis, Thomas D. Weigold, Thomas P. Parnell
  • Patent number: 10235283
    Abstract: A technique for supporting in-place updates in a data storage system includes in response to garbage collection for a logical block address (LBA) being indicated, determining whether an in-place update to the LBA is pending. In response to one or more in-place updates to the LBA being pending prior to the garbage collection for the LBA being indicated, the garbage collection for the LBA is initiated following completion of the one or more in-place updates to the LBA. In response to the one or more in-place updates to the LBA not being pending prior to the garbage collection for the LBA being indicated, the garbage collection for the LBA is completed prior to any subsequent in-place update to the LBA that occurs subsequent to initiation and prior to completion of the garbage collection for the LBA.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zah Barzik, Nikolas Ioannou, Ioannis Koltsidas, Amit Margalit
  • Patent number: 10222998
    Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10222997
    Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic