Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: A method of forming a phase change memory device is provided. The method includes depositing an electrode layer on a phase change material core, and forming a sacrificial layer on the electrode layer. The method further includes depositing a planarization layer on the sacrificial layer, and depositing an anti-reflective coating on the planarization layer. The method further includes forming a template on the anti-reflective coating, and removing a portion of the anti-reflective coating, a portion of the planarization layer, and a portion of the sacrificial layer to form a reduced height sacrificial layer and a sacrificial layer section beneath the planarization layer section. The method further includes removing the anti-reflective coating section and planarization layer section to expose the sacrificial layer section, and removing the reduced height sacrificial layer and a portion of the electrode layer to form a top electrode on the phase change material core.

Abstract: Techniques for forming barrierless contacts filled with Co are provided. In one aspect, a method for forming barrierless contacts includes: forming bottom metal contacts in a first ILD; depositing a second ILD on the bottom metal contacts; forming contact vias in the second ILD landing on the bottom metal contacts; selectively forming a liner on a top surface of the second ILD and on the second ILD along sidewalls of the contact vias; filling the contact vias with a metal; and removing an excess of the metal to form the barrierless contacts whereby metal-to-metal contact is present between the barrierless contacts and the bottom metal contacts. A contact structure is also provided.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield.

Abstract: A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.

Abstract: A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.

Abstract: Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield.