ENHANCED LATERAL CAVITY ETCH
A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.
This application is a divisional of U.S. Nonprovisional Patent Application Ser. No. 14/973,904, filed Dec 18, 2015, the contents of which are herein incorporated by reference in its entirety.
FIELD OF THE INVENTIONThis invention relates to the field of semiconductor devices and more specifically to the formation of a cavity wherein the width of the cavity exceeds the depth in a semiconductor device.
BACKGROUNDCavities are frequently formed in semiconductor circuits to reduce coupling of a device such as an inductor, heater, or bolometer to the substrate. Typically a cavity is etched into a substrate material such silicon or SiGe through an opening in a dielectric layer overlying the substrate using a substantially isotropic etch. Typically the substantially isotropic etch, etches the cavity vertically faster than it does laterally. Consequently a very deep cavity may need to be formed to completely remove the substrate laterally from under the device to reduce coupling. The deep cavity may weaken the substrate resulting in breakage and yield loss.
One method to avoid etching a deep cavity is to build an etch stop layer into the substrate under the device with the coupling issue. This method may add significant complexity, cycle time, and cost to the manufacturing flow.
SUMMARYThe following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
A cavity is formed in a semiconductor substrate wherein the width of the cavity is greater than the depth of the cavity and wherein the depth of the cavity is non uniform across the width of the cavity. The cavity may be formed under an electronic device in the semiconductor substrate. The cavity is formed in the substrate by performing a first cavity etch followed by repeated cycles of polymer deposition, cavity etch, and polymer removal.
The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
A structure with a cavity that is etched according to embodiments is illustrated in
The method for forming a cavity wherein the width of the cavity is substantially wider than the depth of the cavity is described in the process flow in
In first cavity etch step 202 of
Example cavity etch process conditions are 225 mT pressure, 4000 Watts source power, 0 Watts bias power, 1000 sccm SF6, and a temperature of 15° C.
In step 204 of
Example polymer deposition process conditions are 10 mT pressure, 3800 Watts source power, 0 Watts bias power, 200 sccm C4F8, and a temperature of 15° C.
In step 206 of
Example ashing process conditions are 30 mT pressure, 2500 Watts source power, 0 Watts bias power, 200 sccm oxygen, and a temperature of 15° C.
In step 208 of
In step 210 of
In step 212 of
If, however, the target cavity width is not achieved, the wafers may be returned to step 204 in
A second polymer deposition step followed by a third cavity etch is illustrated in
In
In
In
In
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Claims
1. A semiconductor device comprising a cavity in a substrate wherein the cavity is wider than it is deep and wherein a depth of the cavity is non-uniform across a width of the cavity.
2. The semiconductor device of claim 1, wherein the substrate is single crystal silicon.
3. The semiconductor device of claim 1, wherein the substrate is single crystal silicon germanium.
4. The semiconductor device of claim 1, wherein the cavity underlies an opening in an overlying masking layer.
5. The semiconductor device of claim 4, wherein the masking layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.
6. The semiconductor device of claim 1, wherein the cavity is under an inductor.
7. The semiconductor device of claim 1, wherein the cavity is under a bolometer.
8. The semiconductor device of claim 1, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
9. A semiconductor device comprising:
- a silicon substrate without an etch stop layer within the silicon substrate;
- a cavity in the silicon substrate wherein the cavity is at least twice as wide as it is deep.
10. The semiconductor device of claim 9, wherein the silicon substrate is single crystal silicon.
11. The semiconductor device of claim 9, wherein the silicon substrate is single crystal silicon germanium.
12. The semiconductor device of claim 9, wherein the cavity is under an inductor.
13. The semiconductor device of claim 9, wherein the cavity is under a bolometer.
14. The semiconductor device of claim 9, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
15. A semiconductor device comprising:
- a substrate of single crystal silicon;
- a cavity in the substrate wherein the cavity is at least twice as wide as it is deep, wherein single crystal silicon forms a bottom surface and side surfaces of the cavity and wherein a depth of the cavity is non-uniform across a width of the cavity.
16. The semiconductor device of claim 15, wherein the cavity is under an inductor.
17. The semiconductor device of claim 15, wherein the cavity is under a bolometer.
18. The semiconductor device of claim 15, wherein the cavity is under an electronic device that is sensitive to capacitive coupling to the substrate.
Type: Application
Filed: Feb 10, 2017
Publication Date: Jun 22, 2017
Inventors: Brian E. Goodlin (Plano, TX), Karen H. R. Kirmse (Richardson, TX), Iqbal R. Saraf (Wappingers Falls, NY)
Application Number: 15/429,403