Patents by Inventor Iqbal Rajwani
Iqbal Rajwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200294180Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: Altug Koker, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Josh Mastronarde, Naveen Matam, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
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Publication number: 20200294181Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
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Patent number: 10747286Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: GrantFiled: June 11, 2018Date of Patent: August 18, 2020Assignee: INTEL CORPORATIONInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Publication number: 20190377395Abstract: Embodiments are generally directed to dynamic power budget allocation in a multi-processor system. An embodiment of an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.Type: ApplicationFiled: June 11, 2018Publication date: December 12, 2019Applicant: Intel CorporationInventors: Nikos Kaburlasos, Iqbal Rajwani, Bhushan Borole, Kamal Sinha, Sanjeev Jahagirdar
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Patent number: 10491217Abstract: An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).Type: GrantFiled: August 9, 2018Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Steven Hsu, Amit Agarwal, Simeon Realov, Iqbal Rajwani, Ram K. Krishnamurthy
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Patent number: 10333379Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.Type: GrantFiled: December 16, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A Thaploo, Surya Sasi Kiran Tallapragada, Daivik H Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Publication number: 20190044511Abstract: An apparatus is provided which comprises: a first inverter to receive a clock; a pass-gate coupled to the first inverter; a second inverter coupled to the pass-gate and to provide an output clock; and a device coupled to the second inverter and the pass-gate, wherein the transistor and the pass-gate are controllable by a logic that depends on logic values of at least two signals (e.g., an enable and the clock).Type: ApplicationFiled: August 9, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Steven HSU, Amit AGARWAL, Simeon REALOV, Iqbal RAJWANI, Ram K. KRISHNAMURTHY
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Publication number: 20180175832Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Suphachai Chai Sutanthavibul, Iqbal Rajwani, Anupama A. Thaploo, Surya Sasi Tallapragada, Daivik H. Bhatt, Lei Jiang, Stephen Kim, Pascal A. Meinerzhagen, Muhammad M. Khellah
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Patent number: 9685208Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.Type: GrantFiled: April 8, 2016Date of Patent: June 20, 2017Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
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Publication number: 20160225419Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
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Patent number: 9355694Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.Type: GrantFiled: March 28, 2014Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
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Publication number: 20150279438Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.Type: ApplicationFiled: March 28, 2014Publication date: October 1, 2015Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
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Patent number: 7130236Abstract: In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.Type: GrantFiled: March 16, 2005Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: Iqbal Rajwani, Satish Damaraju
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Publication number: 20060209606Abstract: In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.Type: ApplicationFiled: March 16, 2005Publication date: September 21, 2006Inventors: Iqbal Rajwani, Satish Damaraju