Patents by Inventor Ira Naot
Ira Naot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7754564Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: GrantFiled: March 12, 2008Date of Patent: July 13, 2010Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Assaf Lahav, Ira Naot, Yakov Roizin
-
Patent number: 7671396Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: GrantFiled: January 4, 2006Date of Patent: March 2, 2010Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Asaf Lahav, Ira Naot, Yakov Roizin
-
Patent number: 7575977Abstract: An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.Type: GrantFiled: March 26, 2007Date of Patent: August 18, 2009Assignee: Tower Semiconductor Ltd.Inventors: Sharon Levin, Ira Naot, Alexei Heiman
-
Patent number: 7544557Abstract: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.Type: GrantFiled: October 21, 2005Date of Patent: June 9, 2009Assignee: Tower Semiconductor Ltd.Inventors: Sharon Levin, Shye Shapira, Ira Naot, Robert J. Strain, Yossi Netzer
-
Patent number: 7485941Abstract: A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi2) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode. The surrounding buried N-well is coupled to a bias voltage. The Schottky barrier and backside contact structures are separated by isolation structures formed using polycrystalline silicon, which is used to form the gate structure of CMOS FETs, in order to minimize forward resistance. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.Type: GrantFiled: October 21, 2005Date of Patent: February 3, 2009Assignee: Tower Semiconductor Ltd.Inventors: Sharon Levin, Shye Shapira, Ira Naot, Robert J. Strain, Yossi Netzer
-
Publication number: 20090011576Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.Type: ApplicationFiled: September 10, 2008Publication date: January 8, 2009Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Yosi Netzer, Ira Naot, Myriam Buchbinder, Avi Ben-Guigui
-
Publication number: 20080242033Abstract: An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Applicant: Tower Semiconductor Ltd.Inventors: Sharon Levin, Ira Naot, Alexei Heiman
-
Patent number: 7397088Abstract: A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).Type: GrantFiled: March 27, 2006Date of Patent: July 8, 2008Assignee: Tower Semiconductor Ltd.Inventors: Ira Naot, Yaron Blecher
-
Publication number: 20080160689Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Applicant: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Assaf Lahav, Ira Naot, Yakov Roizin
-
Publication number: 20070223162Abstract: A lateral bipolar transistor is used to protect a passive radio frequency (RF) microelectronic circuit during electrostatic discharge (ESD) events. The microelectronic circuit receives a high frequency differential input signal across first and second pads. The lateral bipolar transistor includes an n-type emitter coupled to the first pad and an n-type collector coupled to the second pad. The emitter and collector are located in a p-well, which forms the base of the transistor. The p-well is located in an isolating n-well, which in turn, is located in a p-type substrate. The n-well is coupled to receive the VDD supply voltage and the p-substrate is coupled to a VSS reference voltage. A dielectric region can be located between the emitter and collector (in the p-well).Type: ApplicationFiled: March 27, 2006Publication date: September 27, 2007Applicant: Tower Semiconductor Ltd.Inventors: Ira Naot, Yaron Blecher
-
Publication number: 20070166912Abstract: A capacitor for a single-poly floating gate device is fabricated on a semiconductor substrate along with low and high voltage transistors. Each transistor has a gate width greater than or equal to a minimum gate width of the associated process. A dielectric layer is formed over the substrate, and a patterned polysilicon structure is formed over the dielectric layer. The patterned polysilicon structure includes one or more narrow polysilicon lines, each having a width less than the minimum gate width. The LDD implants for low and high voltage transistors of the same conductivity type are allowed to enter the substrate, using the patterned polysilicon structure as a mask. A thermal drive-in cycle results in a continuous diffusion region that merges under the narrow polysilicon lines. Contacts formed adjacent to the narrow polysilicon lines and a metal-1 trace connected to the contacts may increase the resulting capacitance.Type: ApplicationFiled: January 4, 2006Publication date: July 19, 2007Applicant: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Zohar Kuritsky, Asaf Lahav, Ira Naot, Yakov Roizin
-
Publication number: 20060255398Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.Type: ApplicationFiled: January 23, 2006Publication date: November 16, 2006Applicant: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Yosi Netzer, Ira Naot, Myriam Buchbinder, Avi Ben-Guigui
-
Publication number: 20060125039Abstract: A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.Type: ApplicationFiled: May 23, 2005Publication date: June 15, 2006Applicant: Tower Semiconductor Ltd.Inventors: Sharon Levin, Shye Shapira, Ira Naot
-
Publication number: 20060125040Abstract: A Schottky diode is formed on an isolated well (e.g., a P-well formed in a buried N-well), and utilizes cobalt silicide (CoSi2) structures respectively formed on heavily doped and lightly doped regions of the isolated well to provide the Schottky barrier and backside (ohmic) contact structures of the Schottky diode. The surrounding buried N-well is coupled to a bias voltage. The Schottky barrier and backside contact structures are separated by isolation structures formed using polycrystalline silicon, which is used to form the gate structure of CMOS FETs, in order to minimize forward resistance. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.Type: ApplicationFiled: October 21, 2005Publication date: June 15, 2006Applicant: Tower Semiconductor Ltd.Inventors: Sharon Levin, Shye Shapira, Ira Naot, Robert Strain, Yossi Netzer
-
Publication number: 20060125019Abstract: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.Type: ApplicationFiled: October 21, 2005Publication date: June 15, 2006Applicant: Tower Semiconductor Ltd.Inventors: Sharon Levin, Shye Shapira, Ira Naot, Robert Strain, Yossi Netzer