Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. One embodiment includes placing multiple semiconductor chips onto a carrier, each of the semiconductor chips having a first face and a second face opposite to the first face. An encapsulation material is applied over the multiple semiconductor chips and the carrier to form an encapsulating body having a first face facing the carrier and a second face opposite to the first face. A redistribution layer is applied over the multiple semiconductor chips and the first face of the encapsulating body. An array of external contact elements are applied to the second face of the encapsulating body.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: The semiconductor device comprises a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulating the semiconductor chip, the encapsulating body having a first face and a second face opposite to the first face, a redistribution layer extending over the semiconductor chip and the first face of the encapsulating body and containing a metallization layer comprising contact areas connected with the contact elements of the semiconductor chip, and an array of external contact elements located on the second phase of the encapsulating body.

Abstract: One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process.

Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.

Abstract: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip having an integrated circuit, a functional element electrically coupled with the integrated circuit, and an array of contact elements connected with the integrated circuit and the functional element. The functional element is configured to protect the integrated circuit from transient voltage.

Abstract: A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are arranged in the volume of the solder material.

Abstract: The semiconductor device comprises a semiconductor chip defining a first face and a second face opposite to the first face, the semiconductor chip comprising at least one contact element on the first face of the semiconductor chip, an encapsulating body encapsulating the semiconductor chip, the encapsulating body having a first face and a second face opposite to the first face, a redistribution layer extending over the semiconductor chip and the first face of the encapsulating body and containing a metallization layer comprising contact areas connected with the contact elements of the semiconductor chip, and an array of external contact elements located on the second phase of the encapsulating body.

Abstract: One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process.

Abstract: A semiconductor package includes a semiconductor chip having an integrated circuit, a functional element electrically coupled with the integrated circuit, and an array of contact elements connected with the integrated circuit and the functional element. The functional element is configured to protect the integrated circuit from transient voltage.

Abstract: For the vertical electrical connection of a number of components, an electronic structure with at least two components has solderable connecting elements, which include at least one socket element and a solder ball stacked on the socket element. The socket element has a cylindrical core of an electrically conducting first material with a lateral surface, a bottom surface and a top surface. The core is surrounded with a cladding of an electrically insulating second material in such a way that the lateral surface of the core is covered by the cladding and the top surface and the bottom surface are kept free of the cladding.

Abstract: A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.

Abstract: A carrier sheet with an adhesive film includes a heat-resistant base film with an upper side and an underside, and a thermoactive adhesive layer arranged on the underside of the base film and oriented toward the carrier sheet. The upper side of the base film includes an adhesive layer with semiconductor chips fixed on it, the semiconductor chips being surrounded by deactivated regions of the adhesive layer of the film upper side.

Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.