Abstract: Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data.

Abstract: Generally speaking, methods and apparatuses which correct errors related to phase and gain imbalances in quadrature tuners are disclosed. The quadrature tuner may be online and operating, receiving data. An embodiment may generate a squared signal from the IF frequency signal of the tuner. In generating the squared signal, the embodiment may enable the extraction of phase error and gain error information of the IF signal. The embodiment may determine a phase error component, a gain error component, or both, by frequency translation. The frequency translation may involve down-converting the signal associated with the error component to direct current (DC) signals and enable the determination of the associated phase error and/or gain error. The embodiments may generate an adjusted signal via the IF signal by applying a phase correction signal or gain correction signal to components used to correct the IF signal.

Abstract: According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample.

Abstract: A system for amplifying a signal with active power management according to one embodiment includes a first digital to analog converter (DAC) circuit configured to provide a modulated carrier signal; a amplifier circuit coupled to the first DAC, where the amplifier circuit is configured to amplify the modulated carrier signal; an output stage circuit coupled to the amplifier circuit, where the output stage circuit is configured to provide the amplified signal to a network; a second DAC circuit configured to provide a full wave rectified envelope of the modulated carrier signal; and a switching regulator circuit including a voltage reference input coupled to the second DAC circuit, where the switching regulator circuit is configured to provide a supply voltage to the output stage circuit and the supply voltage is modulated in response to the envelope received at the voltage reference input.

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract: Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data.

Abstract: A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.

Abstract: A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.

Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

Abstract: Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range.

Abstract: Generally, this disclosure describes an apparatus, systems and methods for adaptively controlling a voltage regulator.

Abstract: Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.

Abstract: Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data.

Abstract: Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes.

Abstract: Various embodiments are directed to apparatuses and methods to reduce average power dissipation in transceiver stages such as power amplifiers and low noise amplifiers (LNAs) that process signals of varying output amplitudes. Power dissipation may be reduced by varying the supply voltage in sympathy with the amplitude of the signal and/or the stage current density which may also be varied in sympathy with the signal amplitude.

Abstract: An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.

Abstract: A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.

Abstract: Logic such as hardware and/or code for high-speed analog-to-digital conversion of a signal. Logic may receive an analog signal as an input to a sampling receiver. The sampling receiver may implement a successive approximation register (SAR), analog-to-digital converter (ADC) to produce the digital output. Logic may re-task a comparator of the SAR ADC during a sampling mode to generate a digital comparator output that represents a comparison of a voltage of the charge on a capacitance of the DAC against a threshold reference voltage. The digital comparator output may be applied to the input of automatic gain control (AGC) logic. The AGC logic may receive the digital comparator signal which is representative of one sample of a multiple sample, sample cycle, allowing the AGC logic to generate a gain control signal that is responsive to both total composite average and peak amplitudes.

Abstract: According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample.

Abstract: Embodiments may comprise logic such as hardware and/or code for high-speed digital-to-analog conversion of signals. Many embodiments comprise a demultiplexer to distribute sets of bits to digital-to-analog converters, the digital-to-analog converters to receive the sets of bits and the operate concurrently to convert the sets of bits from digital representations of signal segments to output analog signal segments, and an interleaver to interleave the analog signal segments from each of digital-to-analog converters in the sequence to generate an analog signal. In many embodiments, the interleaver is adapted to interleave the analog signal segments by latching magnitudes of each of the analog signal segments to an interleaved output near ends of clock cycles to attenuate non-linearities in the magnitudes of each of the analog signal segments when the magnitudes are output.