Abstract: A nonvolatile memory device has a first insulating layer, a variable resistance layer provided on the first insulating layer and having a variable resistance material, and a first electrode and second electrode electrically connected with the variable resistance layer. The variable resistance layer has a variable resistance region as a data storing region and a thickness-changing region continuously extending from the variable resistance region and gradually becoming thicker from the variable resistance region.

Abstract: A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.

Abstract: A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.

Abstract: A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13.

Abstract: The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.

Abstract: A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording layer. With this arrangement, a contact area between the recording layer and the upper electrode and a contact area between the upper electrode and the bit line can be reduced without providing an interlayer insulation film between the upper electrode and the bit line. Thus, heat radiation to the bit line can be suppressed while the upper electrode and the bit line are connected without using a through-hole.

Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

Abstract: In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.

Abstract: A non-volatile memory element includes a bottom electrode 12, a bit line 14 provided on the bottom electrode 12, and a recording layer 15 containing phase change material connected between the bottom electrode 12 and the bit line 14. In accordance with this invention, the bit line 14 is in contact with a growth initiation surface 15a of the recording layer 15. This structure can be obtained by forming the bit line 14 before the recording layer 15, resulting in a three-dimensional structure. This decreases the area of contact between the recording layer 15 and the bit line 14, decreasing heat dissipation to the bit line 14 without increasing the thickness of the recording layer 15. With this three-dimensional structure, moreover, there is no top electrode between the bit line 14 and the recording layer 15, keeping down the complexity of the fabrication process.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced in order to lower the power consumption of a variable resistance memory device. The present invention provides a method of producing a variable resistance memory element whereby the lower electrode can be more finely formed. The method of producing a semiconductor device according to the present invention includes forming a small opening by utilizing cubical expansion due to the oxidation of silicon. Thereby forming the lower electrode smaller than that can be formed by lithography techniques.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

Abstract: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: A multi-layer chalcogenide, memory or switching device. The device includes an active region disposed between a first terminal and a second terminal. The active region includes a first layer and a second layer, where one of the layers is a heterogeneous layer that includes an operational component and a promoter component. The other layer may be a homogeneous or heterogeneous layer. In exemplary embodiments, the operational component is a chalcogenide or phase change material and the promoter component is an insulating or dielectric material. Inclusion of the promoter component provides beneficial performance characteristics such as a reduction in reset current or minimization of formation requirements.

Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

Abstract: Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode or before power down and data is transferred from the area of the non-volatile memory to the DRAM memory array in exiting from the data retention mode or power up. Normal read/write access is made to the DRAM memory array, while data retention is in an area of the non-volatile memory.

Abstract: A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided between the bottom electrode 12 and the top electrode 15. The block layer 14 is constituted of material having an electrical resistance that is higher than that of material constituting the recording layer 13. The block layer 14 suppresses the radiation of heat towards the top electrode 15 and greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.

Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.