Patents by Inventor Isao Kamioka
Isao Kamioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8404537Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.Type: GrantFiled: June 4, 2012Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Publication number: 20120282773Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.Type: ApplicationFiled: June 4, 2012Publication date: November 8, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Publication number: 20120122294Abstract: In one embodiment, a method of manufacturing a semiconductor device includes successively forming first and second films to be processed on a semiconductor substrate. The method further includes removing a predetermined region of the second film by etching, to form a slit part including sidewall parts and a bottom part, the sidewall parts including side surfaces of the second film, and the bottom part including an upper surface of the first film. The method further includes supplying oxidizing ions or nitriding ions contained in plasma, generated by a microwave, a radio-frequency wave, or electron cyclotron resonance, to the sidewall parts and the bottom part of the slit part by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the slit part.Type: ApplicationFiled: December 15, 2011Publication date: May 17, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Patent number: 8115249Abstract: In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride is formed between the charge block layer and each of the control gate electrode, the cap layer being divided for each gate control electrode.Type: GrantFiled: September 21, 2009Date of Patent: February 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Yoshio Ozawa, Katsuyuki Sekine
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Patent number: 8097503Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.Type: GrantFiled: November 12, 2010Date of Patent: January 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Patent number: 8093126Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.Type: GrantFiled: March 17, 2010Date of Patent: January 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
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Patent number: 8026133Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.Type: GrantFiled: June 24, 2009Date of Patent: September 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka
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Patent number: 7927949Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: GrantFiled: April 7, 2010Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Publication number: 20110065262Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.Type: ApplicationFiled: November 12, 2010Publication date: March 17, 2011Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Patent number: 7897455Abstract: A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate containing silicon, the first insulating film having a first dielectric constant and constituting a part of a tunnel insulating film, forming a floating gate electrode film on the first insulating film, the floating gate electrode film being formed of a semiconductor film containing silicon, patterning the floating gate electrode film, the first insulating film, and the semiconductor substrate to form a first structure having a first side surface, exposing the first structure to an atmosphere containing an oxidizing agent, oxidizing that part of the floating gate electrode film which corresponds to a boundary between the first insulating film and the floating gate electrode film using the oxidizing agent, to form a second insulating film having a second dielectric constant smaller than the first dielectric constant and constituting a part of the tunnel insulating film.Type: GrantFiled: September 22, 2006Date of Patent: March 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka
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Patent number: 7883967Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.Type: GrantFiled: July 24, 2006Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
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Patent number: 7858467Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.Type: GrantFiled: March 27, 2009Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Publication number: 20100197130Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: ApplicationFiled: April 7, 2010Publication date: August 5, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Yoshio OZAWA, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Publication number: 20100171169Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.Type: ApplicationFiled: March 17, 2010Publication date: July 8, 2010Inventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
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Publication number: 20100140682Abstract: In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride is formed between the charge block layer and each of the control gate electrode, the cap layer being divided for each gate control electrode.Type: ApplicationFiled: September 21, 2009Publication date: June 10, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Isao KAMIOKA, Yoshio OZAWA, Katsuyuki SEKINE
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Patent number: 7723772Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: GrantFiled: January 30, 2007Date of Patent: May 25, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Publication number: 20100087041Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film on the exposed surface of the first insulating film in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and then unloading the semiconductor substrate from the first processing chamber to the outside; and annealing the second insulating film in a second processing chamber.Type: ApplicationFiled: December 2, 2009Publication date: April 8, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Yoshio Ozawa
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Patent number: 7645711Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film on the exposed surface of the first insulating film in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and then unloading the semiconductor substrate from the first processing chamber to the outside; and annealing the second insulating film in a second processing chamber.Type: GrantFiled: April 15, 2005Date of Patent: January 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Yoshio Ozawa
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Publication number: 20090269894Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer.Type: ApplicationFiled: June 24, 2009Publication date: October 29, 2009Inventors: Yoshio Ozawa, Isao Kamioka
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Publication number: 20090246932Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.Type: ApplicationFiled: March 27, 2009Publication date: October 1, 2009Inventors: Isao KAMIOKA, Junichi SHIOZAWA, Ryu KATO, Yoshio OZAWA