Patents by Inventor Isao Ozawa

Isao Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140175021
    Abstract: Provided are a system and a method for treating ballast water for a ship, the system including a rotary filtration apparatus including a filter that is cylindrically formed so as to surround an axis, that is rotatable around the axis, and that has a pleated shape that is folded in a cylinder radial direction; and an electric motor for rotating the filter. A distance between the cleaning nozzle and a recess of the filter is 120 mm or less. The system and the method are configured to perform a steady-state operation that satisfies the following conditions a to d: a) a rotation speed of the filter during a filtering operation is in the range of 20 to 100 rpm, b) a flow speed of cleaning water ejected from the cleaning nozzle is 250 m/min or more, c) a flow rate of filtered water per unit area of the filter is 5.1 m/h or less, and d) a flow rate of discharged water discharged from the discharge channel is 5% of the flow rate of filtered water or more.
    Type: Application
    Filed: February 8, 2013
    Publication date: June 26, 2014
    Inventors: Munetsugu Ueyama, Isao Ozawa, Kenichiro Miyatake, Ryusuke Nakai
  • Publication number: 20130319953
    Abstract: A ballast water treatment apparatus includes a filter that is cylindrically formed so as to surround an axis, a case that includes an outer cylindrical portion that is disposed so as to surround the filter, a rotation mechanism that rotates the filter around the axis, an untreated water nozzle that ejects untreated water to a filter-surrounding region that is defined by an outer peripheral surface of the filter and the outer cylindrical portion, a cleaning water nozzle that ejects cleaning water toward the outer peripheral surface of the filter, a filtered water channel through which filtered water that has passed through the filter flows from a region inside the filter to outside of the case, and a discharge channel through which discharged water that has not passed through the filter is discharged from the filter-surrounding region to outside of the case.
    Type: Application
    Filed: July 23, 2012
    Publication date: December 5, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Isao Ozawa, Munetsugu Ueyama, Ryusuke Nakai
  • Publication number: 20130187272
    Abstract: According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire.
    Type: Application
    Filed: July 26, 2012
    Publication date: July 25, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Isao OZAWA
  • Publication number: 20120326338
    Abstract: According to one embodiment, a semiconductor device is provided which includes a substrate in which conductor layers and insulated layers are stacked alternately, a semiconductor element mounted on a first surface side of the substrate, and a reinforcing plate attached to a second surface side that is an opposite side of the first surface of the substrate.
    Type: Application
    Filed: June 27, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toyokazu EGUCHI, Manabu Matsumoto, Isao Ozawa
  • Publication number: 20120210049
    Abstract: According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 16, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki NAGAHARA, Isao Ozawa
  • Patent number: 8131912
    Abstract: A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Ozawa, Takashi Oshima
  • Publication number: 20110133323
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: February 17, 2011
    Publication date: June 9, 2011
    Inventor: Isao OZAWA
  • Patent number: 7919837
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: April 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Ozawa
  • Publication number: 20100007014
    Abstract: According to an aspect of the invention, a semiconductor device includes: a semiconductor substrate; a memory chip disposed on the semiconductor substrate, the memory chip including: a first face that is not opposed to the semiconductor substrate; and a plurality of first pads disposed on the first face so that the first pads are aligned along a virtual line passing at a central portion on the first face; a controller chip disposed on the first face not to cover the first pads, the controller chip including: a second face that is not opposed to the first face; and a plurality of second pads disposed on the second face so that the second pads are aligned along at least one side of the second face; and a plurality of metal wires electrically connecting the first pads and the second pads.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 14, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hidetoshi Suzuki, Isao Ozawa, Atsushi Kaneko, Yuka Matsunaga
  • Publication number: 20090089490
    Abstract: A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Isao OZAWA, Takashi OSHIMA
  • Patent number: 7495329
    Abstract: A semiconductor memory card includes a nonvolatile memory chip mounted on an upper surface of a circuit board. The memory chip has first bonding pads formed close to a first side of the memory chip that are wire-bonded to first board terminals formed on the board along the first side. A controller chip mounted on the memory chip has second bonding pads wire-bonded to second board terminals formed on the board along a second side of the memory chip, adjacent to the first side. A power terminal or a ground terminal has a connection and an extension extended from the connection. The connection and the extension are along the first board terminals and the second board terminals. The connection and the extension are on a lower surface of the board and connect to the first board terminals or the second board terminals via through hole interconnections and the board wiring.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: February 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yohichi Ohta, Isao Ozawa
  • Publication number: 20090026630
    Abstract: The present invention provides a semiconductor device capable of preventing chip cracks in a manufacturing process as much as possible, wherein the semiconductor device includes: a substrate main body provided with an inner surface internal to the semiconductor device and an outer surface external to the semiconductor device opposed to each other; an external wiring pattern having a pattern for non-external terminals covered with an insulating material and a pattern for external terminals electrically conductive to the outside formed at least on the outer surface of the substrate main body using a conductive material and electrically connected to each other; an insulating film for covering the pattern for non-external terminals of the external wiring pattern; a metal-plated layer adapted to constitute external terminals in conjunction with the pattern for external terminals and formed on the pattern for external terminals of the external wiring pattern, so as to reduce or eliminate a difference in step with r
    Type: Application
    Filed: July 25, 2008
    Publication date: January 29, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Isao OZAWA, Youichi Oota
  • Patent number: 7339257
    Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Ozawa, Akihito Ishimura, Yasuo Takemoto, Tetsuya Sato
  • Publication number: 20070170567
    Abstract: A semiconductor memory card which inputs/outputs signals by connecting to an external device, has a circuit board on an upper surface of which board terminals connected to board wiring are formed, and on a lower surface of which input/output card terminals for inputting/outputting signals to/from the external device, a power supply card terminal for supplying electric power, and a ground card terminal connected to ground potential by connecting to the external device are provided; a nonvolatile memory chip which is mounted on the upper surface of the circuit board, and has a plurality of first bonding pads formed close to a first side of the nonvolatile memory chip in a manner that the plurality of first bonding pads are wire-bonded to a plurality of first board terminals formed on the circuit board along the first side; and a controller chip which is mounted on the nonvolatile memory chip, and has a plurality of second bonding pads formed in a manner that the plurality of second bonding pads are wire-bonded
    Type: Application
    Filed: January 22, 2007
    Publication date: July 26, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yohichi Ohta, Isao Ozawa
  • Publication number: 20060255436
    Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 16, 2006
    Inventor: Isao Ozawa
  • Publication number: 20060145329
    Abstract: A lead frame for semiconductor device has at least one bed frame capable of supporting a dual-pin-type chip, a plurality of suspension pin frames which extend from the bed frame in a first direction, and are disposed apart from each other in a second direction, and at least two beam frames which extend from the plurality of suspension pin frames in the second direction, and connect the plurality of suspension pin frames at both sides of the chip by sandwiching the chip.
    Type: Application
    Filed: December 9, 2005
    Publication date: July 6, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Isao Ozawa
  • Patent number: 6995320
    Abstract: A wiring board includes an insulating board defined by a first surface and a second surface opposing to the first surface; first signal strips disposed on the first surface; a first power distribution plane provided on the first surface so as to occupy a residual area of the first signal strips; lands disposed on the second surface; via metals penetrating the insulating board so as to connect the lands to the corresponding first signal strips; a second power distribution plane provided on the second surface.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kusakabe, Isao Ozawa
  • Publication number: 20050236698
    Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.
    Type: Application
    Filed: April 26, 2005
    Publication date: October 27, 2005
    Inventors: Isao Ozawa, Akihito Ishimura, Yasuo Takemoto, Tetsuya Sato
  • Patent number: D673921
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Isao Ozawa
  • Patent number: D673922
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takakatsu Moriai, Isao Ozawa, Toyokazu Eguchi