Patents by Inventor Iwao Kunishima

Iwao Kunishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6586790
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: July 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kanaya, Iwao Kunishima, Koji Yamakawa, Tsuyoshi Iwamoto, Hiroshi Mochizuki
  • Publication number: 20020075736
    Abstract: Provided are a semiconductor memory device that permits increasing the degree of integration without decreasing the capacitance of the capacitor included in a memory cell, and a method of manufacturing the particular semiconductor memory device. Specifically, provided are a semiconductor memory device, comprising a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, a first electrode formed on the interlayer insulating film, a first ferroelectric film formed on the first electrode, a second electrode formed on the first ferroelectric film, a second ferroelectric film formed on the second electrode, and a third electrode formed on the second ferroelectric film, and a method of manufacturing the particular semiconductor memory device.
    Type: Application
    Filed: November 19, 2001
    Publication date: June 20, 2002
    Inventors: Yoshinori Kumura, Hiroyuki Kanaya, Iwao Kunishima
  • Publication number: 20020063274
    Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.
    Type: Application
    Filed: July 23, 1999
    Publication date: May 30, 2002
    Inventors: HIROYUKI KANAYA, IWAO KUNISHIMA, KOJI YAMAKAWA, TSUYOSHI IWAMOTO, HIROSHI MOCHIZUKI
  • Publication number: 20020033494
    Abstract: A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.
    Type: Application
    Filed: September 20, 2001
    Publication date: March 21, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tohru Ozaki, Iwao Kunishima, Toyota Morimoto, Hiroyuki Kanaya
  • Patent number: 6190957
    Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
  • Patent number: 6140247
    Abstract: A semiconductor device manufacturing method includes the step of forming a silicon oxide film on the surface of a silicon region, and the step of supplying anhydrous hydrofluoric acid gas to the silicon oxide film, thereby removing the silicon oxide film. The total concentration of Si--H bonds, Si--O--H bonds, and H.sub.2 O molecules, in the silicon oxide film is 1.times.10.sup.13 /cm.sup.2 or more.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: October 31, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Muraoka, Iwao Kunishima, Hirotaka Nishino
  • Patent number: 6121649
    Abstract: A non-volatile memory has transistors and capacitors formed on a semiconductor substrate. The capacitors have a lower electrode, a ferroelectric film and an upper electrode stacked in order. An insulating film with at least one contact hole is formed on the substrate to cover the gate of each transistor. A side-wall insulating film is also formed to cover the side faces of the lower electrode and the ferroelectric film. A contact electrically connects the upper electrode and the source or drain of each transistor. The side-wall insulating film electrically isolates the contact from the lower electrode. The contact is made of a material at least the portion connected to the upper electrode and the other portion adjacent to that portion. The upper electrode is also made of that material. The upper electrode and the portion of the contact connected to the upper electrode are thus joined each other.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: September 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Iwao Kunishima
  • Patent number: 6018185
    Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: January 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Iwao Kunishima, Masahiro Kashiwagi
  • Patent number: 5990507
    Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: November 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
  • Patent number: 5861675
    Abstract: The tungsten nitride film containing fluorine is used as a barrier metal in the contact hole or via hole of the semiconductor device. The tungsten nitride film formed contains 1% to 20% fluorine at atomic density. With this structure, it is possible to obtain a WNF film having a good step coverage for a fine hole.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: January 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Iwao Kunishima
  • Patent number: 5721175
    Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transition metal compound layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere.
    Type: Grant
    Filed: December 1, 1993
    Date of Patent: February 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Kyoichi Suguro
  • Patent number: 5316977
    Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transitition layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere.
    Type: Grant
    Filed: July 16, 1992
    Date of Patent: May 31, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Kyoichi Suguro
  • Patent number: 5211987
    Abstract: A method for improving the adhesion between a refractory metal film and a silicon substrate is disclosed, which comprises depositing the refractory metal film on the silicon substrate at a first temperature; and heating the contact surface between the deposited film and the silicon surface at a second temperature between 300.degree. and 600.degree. C., wherein the depositing and heating steps are performed in a single reaction furnace and the temperature between the depositing and heating steps does not drop below about 300.degree. C.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Hitoshi Itoh
  • Patent number: 5168332
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further includes metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: December 1, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Tomonori Aoyama, Kyoichi Suguro
  • Patent number: 5162263
    Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type. An insulative film and metal films are sequentially formed on the main top surface of the semiconductor substrate. Impurity diffusion layers of a second conductivity type are selectively formed on the main top surface of the semiconductor substrate. The semiconductor device further comprises metal compound layers consisting of constituting elements of the semiconductor substrate and a metal element. The metal compound layers are formed in the impurity diffusion layers in such a manner that they do not contact the insulative film, and the metal compound layers on the main back surface side of the semiconductor substrate have faces formed in parallel to the top surface of the semiconductor substrate. The method also includes cooling the top of the substrate to form a temperature gradient that results in increased dopant concentration at the bottom of a silicide layer.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: November 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Kunishima, Tomonori Aoyama, Kyoichi Suguro
  • Patent number: 4923715
    Abstract: A method for the formation of a thin, high melting-point metal film such as W, on a substrate surface, by means of CVD, is disclosed herein. In this method, the inner wall of the CVD reaction tube and the surface of the at least part of the fittings disposed therewithin are covered with a metal nitride film, in the process of performing the CVD operation. The method permits the formation of a high quality film, and also prevents the deposition of the high melting-point metal on the inner wall of the reaction chamber, even if the CVD operation is repeatedly performed over a long period of time.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: May 8, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Iwao Kunishima