Patents by Inventor Jacob Subag
Jacob Subag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11132601Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: September 28, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Patent number: 11100393Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: August 24, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Publication number: 20210256272Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Applicant: Intel CorporationInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
-
Patent number: 11093822Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: August 17, 2021Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
-
Patent number: 11087206Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: GrantFiled: April 28, 2017Date of Patent: August 10, 2021Assignee: INTEL CORPORATIONInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Patent number: 11037330Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 8, 2017Date of Patent: June 15, 2021Assignee: INTEL CORPORATIONInventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
-
Publication number: 20210141604Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 24, 2020Publication date: May 13, 2021Applicant: Intel CorporationInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Publication number: 20210049804Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 28, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 10922556Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: February 16, 2021Assignee: INTEL CORPORATIONInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
-
Patent number: 10853035Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 27, 2020Date of Patent: December 1, 2020Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Publication number: 20200293282Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 27, 2020Publication date: September 17, 2020Applicant: Intel CorporationInventors: YANIV Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Patent number: 10762685Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: October 31, 2019Date of Patent: September 1, 2020Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Publication number: 20200143579Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: October 31, 2019Publication date: May 7, 2020Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 10606559Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 12, 2019Date of Patent: March 31, 2020Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Patent number: 10559112Abstract: A mechanism is described for facilitating hybrid rendering of graphics images in computing environments. A method of embodiments, as described herein, includes detecting the video stream including two-dimensional (2D) images, where the video stream is processed through a graphics pipeline at a computing device. The method may further include performing hybrid combination of a luma (Y)-plane with chrominance (UV)-planes to directly generate a YUV texture, wherein the YUV texture is used to generate three-dimensional (3D) images corresponding to the 2D images.Type: GrantFiled: June 10, 2016Date of Patent: February 11, 2020Assignee: INTEL CORPORATIONInventors: Tatiana Surazhsky, Uzi Sarel, Jacob Subag
-
Publication number: 20190361674Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: June 12, 2019Publication date: November 28, 2019Applicant: INTEL CORPORATIONInventors: YANIV FAIS, TOMER BAR-ON, JACOB SUBAG, JEREMIE DREYFUSS, LEV FAIVISHEVSKY, MICHAEL BEHAR, AMIT BLEIWEISS, GUY JACOB, GAL LEIBOVICH, ITAMAR BEN-ARI, GALINA RYVCHIN, EYAL YAACOBY
-
Patent number: 10467795Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 8, 2017Date of Patent: November 5, 2019Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 10372416Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: August 6, 2019Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Publication number: 20180314926Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Applicant: Intel CorporationInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Publication number: 20180314934Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Applicant: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsh, Orly Weisel, Zigi Walter, Yarden Oren