Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to generate synthetic data for a generative adversarial network (GAN) using the plurality of execution units. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to implement training of a deep tree application at a data center. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

Abstract: A mechanism is described for facilitating hybrid rendering of graphics images in computing environments. A method of embodiments, as described herein, includes detecting the video stream including two-dimensional (2D) images, where the video stream is processed through a graphics pipeline at a computing device. The method may further include performing hybrid combination of a luma (Y)-plane with chrominance (UV)-planes to directly generate a YUV texture, wherein the YUV texture is used to generate three-dimensional (3D) images corresponding to the 2D images.

Abstract: Automatic partitioning techniques for multi-phase pixel shading are described. In an example embodiment, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more respective suitability metrics for each of one or more candidate partitioning policies for a set of pixel shader inputs for a graphics frame, each candidate partitioning policy comprising one or more rules for partitioning the set of pixel shader inputs for multi-phase pixel shading based on quality sensitivity values for the pixel shader inputs, select a partitioning policy for the set of pixel shader inputs from among the one or more candidate partitioning policies based on the determined suitability metrics, and construct a multi-phase pixel shader for the graphics frame by partitioning the set of pixel shader inputs into multiple classes according to the selected partitioning policy. Other embodiments are described and claimed.

Abstract: Automatic partitioning techniques for multi-phase pixel shading are described. In an example embodiment, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more respective suitability metrics for each of one or more candidate partitioning policies for a set of pixel shader inputs for a graphics frame, each candidate partitioning policy comprising one or more rules for partitioning the set of pixel shader inputs for multi-phase pixel shading based on quality sensitivity values for the pixel shader inputs, select a partitioning policy for the set of pixel shader inputs from among the one or more candidate partitioning policies based on the determined suitability metrics, and construct a multi-phase pixel shader for the graphics frame by partitioning the set of pixel shader inputs into multiple classes according to the selected partitioning policy. Other embodiments are described and claimed.

Abstract: Techniques are disclosed for carrying out rasterization of a given graphics workload, wherein portions of the workload associated with relatively high bit count operations are processed via a first process path, and portions of the workload associated with relatively lower bit count operations are processed via a second, relatively faster process path, in accordance with an embodiment. In a more general sense, maximal bit count associated with a given primitive can be identified and compared to a threshold to determine which one of multiple available processing paths can be used.

Abstract: Techniques are disclosed for carrying out rasterization of a given graphics workload, wherein portions of the workload associated with relatively high bit count operations are processed via a first process path, and portions of the workload associated with relatively lower bit count operations are processed via a second, relatively faster process path, in accordance with an embodiment. In a more general sense, maximal bit count associated with a given primitive can be identified and compared to a threshold to determine which one of multiple available processing paths can be used.

Abstract: Improved techniques for texture mapping are described. In one embodiment, for example, a host may include a processor circuit and a graphics management module, and the graphics management module may be operable by the processor circuit to determine that a texture value corresponding to a texture coordinate is unavailable, determine a marginal texture coordinate corresponding to the texture coordinate, determine a marginal texture value corresponding to the marginal texture coordinate, and store the marginal texture value in a memory unit. Other embodiments are described and claimed.