Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

Abstract: A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

Abstract: A data receiver includes group envelope detection circuitry that produces a group envelope voltage. The group envelope voltage represents the average envelope of a plurality of amplified data signals. Associated feedback adjusts the gains applied to each data signal to minimize any difference between the group envelope voltage and a reference voltage. The reference voltage is preferably the envelope of a clock signal associated with the data signals.

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and one of a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: An apparatus having a dual rail regulated reference loop. The reference loop includes a delay circuit powered by upper and lower supply voltages to generate a plurality of reference clock signals, and a voltage regulation circuit to adjust the upper and lower supply voltages according to a phase difference between a selected pair of the reference clock signals.

Abstract: A data receiver includes group envelope detection circuitry that produces a group envelope voltage. The group envelope voltage represents the average envelope of a plurality of amplified data signals. Associated feedback adjusts the gains applied to each data signal to minimize any difference between the group envelope voltage and a reference voltage. The reference voltage is preferably the envelope of a clock signal associated with the data signals.

Abstract: A data receiver includes group envelope detection circuitry that produces a group envelope voltage. The group envelope voltage represents the average envelope of a plurality of amplified data signals. Associated feedback adjusts the gains applied to each data signal to minimize any difference between the group envelope voltage and a reference voltage. The reference voltage is preferably the envelope of a clock signal associated with the data signals.