Patents by Inventor Jae-dong Lee

Jae-dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060262641
    Abstract: A slurry delivery system, a chemical mechanical polishing (CMP) apparatus, and method for using the same are provided. An apparatus for supplying slurry to a polishing unit may include a first feed line through which an abrasive may be supplied at a first velocity. A velocity-changing member may be connected to the first feed line, and/or a velocity of the abrasive may be changed from the first velocity to. the second velocity different from the first velocity by the velocity-changing member. A second feed line may be connected to the velocity-changing member and/or an additive may be supplied through the second feed line. A supply line may be connected to the velocity-changing member. A slurry, which may be a mixture of the abrasive and/or the additive, may be supplied to a polishing unit through the supply line. Accordingly, the slurry may be more uniformly mixed and/or supplied to a polishing unit.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 23, 2006
    Inventors: Choong-Kee Seong, Chang-Ki Hong, Jae-Dong Lee
  • Publication number: 20060259525
    Abstract: The present invention provides a recovery method using extendible hashing-based cluster logs in a shared-nothing spatial database cluster, which eliminates the duplication of cluster logs required for cluster recovery in a shared-nothing database cluster, so that recovery time is decreased, thus allowing the shared-nothing spatial database cluster system to continuously provide stable service. In the recovery method, if a failure occurs in a predetermined node, a second node in a group, including the node, records cluster logs in main memory on the basis of extendible hashing. If the node that has failed recovers itself using a local log, the second node in the group transmits cluster logs in packets to a recovery node that is the failed node. If the recovery node reflects the received cluster logs and maintains consistency with other nodes in the group, the recovery node resumes normal service.
    Type: Application
    Filed: June 20, 2005
    Publication date: November 16, 2006
    Inventors: Hae-Young Bae, Jae-Dong Lee, Young-Hwan Oh, Gyoung-Bae Kim, Myoung-Keun Kim, Soon-Young Park, Ho-Seok Kim, Yong-Il Jang
  • Publication number: 20060175297
    Abstract: A metallization method for a semiconductor device, and a cleaning solution for the same, for cleaning a surface of a semiconductor substrate on which a metal wiring material is exposed. The metallization method may include cleaning a surface of a semiconductor substrate on which a metal wiring layer is exposed using a cleaning solution that includes deionized water, an organic acid, and at least one of an anionic surfactant and an amphoteric surfactant, and, after the cleaning, ashing the surface of the metal wiring layer.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 10, 2006
    Inventors: Se-rah Yun, Jeong-heon Park, Chang-ki Hong, Jae-dong Lee
  • Publication number: 20060148258
    Abstract: A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 6, 2006
    Inventors: Se-rah Yun, Chang-ki Hong, Jae-dong Lee
  • Publication number: 20060143993
    Abstract: Slurry compositions and method used in a chemical-mechanical polishing process for manufacturing a semiconductor device may include a surfactant and a positive-ionic high molecular compound. The surfactant and the positive-ionic high molecular compound may form first and second passivation layers on the surface of an exposed polysilicon layer.
    Type: Application
    Filed: January 5, 2006
    Publication date: July 6, 2006
    Inventors: Sung-Jun Kim, Chang-Ki Hong, Jae-Dong Lee, Jae-Kwang Choi
  • Publication number: 20060124594
    Abstract: In one aspect, a chemical-mechanical-polishing (CMP) slurry composition is provided which includes ceria abrasive contained in a solution, where the solution includes a viscosity increasing agent which includes a non-ionic polymer compound, and where a viscosity of the composition is at least 1.5 cP. In other aspects, the viscosity increasing agent includes one or more of poly(ethyleneglycol), a Gum compound and isopropyl alcohol.
    Type: Application
    Filed: November 28, 2005
    Publication date: June 15, 2006
    Inventors: Jong-heun Lim, Jae-dong Lee, Bo-un Yoon, Chang-ki Hong
  • Publication number: 20060037942
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming a surface of a capacitor using the slurry. The slurry may include an abrasive, an oxidizer, and at least one pH controller to control a pH of the slurry.
    Type: Application
    Filed: June 30, 2005
    Publication date: February 23, 2006
    Inventors: Seong-Kyu Yun, Kenichi Orui, Chang-Ki Hong, Jae-Dong Lee, Sung-Jun Kim, Haruki Nojo
  • Publication number: 20060030155
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
    Type: Application
    Filed: March 11, 2005
    Publication date: February 9, 2006
    Inventors: Sung-Jun Kim, Jeong-Heon Park, Chang-Ki Hong, Jae-Dong Lee
  • Publication number: 20050145602
    Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 7, 2005
    Inventors: Jeong-Heon Park, Bo-Un Yoon, Jae-Dong Lee
  • Patent number: 6914001
    Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-won Lee, Jae-dong Lee, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20050130385
    Abstract: A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.
    Type: Application
    Filed: December 9, 2004
    Publication date: June 16, 2005
    Inventors: Jae-Dong Lee, Chang-Ki Hong, Young-Rae Park
  • Publication number: 20050112894
    Abstract: A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon oxide film. A second chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, an oxide film removal retarder which reduces a removal rate of silicon oxide, and a defect prevention agent which inhibits scratch defects and/or corrosion defects at a surface of an aluminum film. In a one-step CMP process, either of the first or second slurry is used throughout CMP of an aluminum layer until an upper surface of an underlying silicon oxide layer is exposed. In a two-step CMP process, the first slurry is used in an initial CMP of the aluminum layer, and then the second slurry is used in a subsequent CMP until the upper surface of the underlying silicon layer is exposed.
    Type: Application
    Filed: October 12, 2004
    Publication date: May 26, 2005
    Inventors: Jeong-heon Park, Jae-dong Lee, Sung-jun Kim, Chang-ki Hong
  • Patent number: 6887137
    Abstract: Slurries for chemical mechanical polishing (CMP) are provided including a high planarity slurry and high selectivity ratio slurry. A high planarity slurry includes at least one kind of metal oxide abrasive particle and an anionic polymer passivation agent having a first concentration. A high selectivity ratio slurry includes at least one kind of the metal oxide abrasive particle, the passivation agent in a second concentration that is less than the first concentration of the passivation agent for the high planarity slurry, one of a quaternary amine and the salt thereof, and a pH control agent. The high selectivity ratio slurry has a pH in a range of about over an isoelectric point of a polishing target layer and less than an isoelectric point of a polishing stopper. In addition, a CMP method using the CMP slurries having high planarity and high selectivity ratio is provided.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: May 3, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-dong Lee, Bo-un Yoon, Yong-pil Han
  • Publication number: 20050075052
    Abstract: For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
    Type: Application
    Filed: September 22, 2004
    Publication date: April 7, 2005
    Inventors: Kwang-Bok Kim, Jae-Kwang Choi, Yong-Sun Ko, Chang-Ki Hong, Kyung-Hyun Kim, Jae-Dong Lee
  • Patent number: 6875997
    Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Heon Park, Bo-Un Yoon, Jae-Dong Lee
  • Patent number: 6863592
    Abstract: CMP (chemical/mechanical polishing) slurries that can rapidly remove a target layer and can effectively passivate a polishing stopper, with high selectivity. In one aspect, a CMP slurry comprises metal oxide abrasive particles, a removal rate accelerator, an anionic polymeric passivation agent having a molecular weight in a range of about 1,000 to about 100,000, a C1-C12 anionic passivation agent, and water.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: March 8, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-won Lee, Chang-ki Hong, Jae-dong Lee
  • Patent number: 6858452
    Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: February 22, 2005
    Assignee: Samsung Electronics Co., LTD
    Inventors: Jeong-heon Park, Chang-ki Hong, Jae-dong Lee, Young-rae Park, Ho-Young Kim
  • Patent number: 6855267
    Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: February 15, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-dong Lee, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20050014330
    Abstract: A method of planarizing an interlayer dielectric layer formed over a one cylinder storage (OCS) capacitor including applying two or three interlayer dielectric layers over the capacitor and planarizing the interlayer dielectric layers using CMP having a different etching selectivity according to the layers.
    Type: Application
    Filed: February 12, 2004
    Publication date: January 20, 2005
    Inventors: Young-Rae Park, Jae-Dong Lee, Joon Park, Chang-Ki Hong
  • Publication number: 20040154231
    Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.
    Type: Application
    Filed: January 15, 2004
    Publication date: August 12, 2004
    Inventors: Jae-dong Lee, Bo-un Yoon, Sang-rok Hah