Abstract: The present invention relates to a complementary metal-oxide-semiconductor (CMOS) image sensor, comprising: a plurality of unit pixel arrayed in rows and columns, wherein the unit pixel including: (a) a charge generating means for generating charges in response to lights reflected from an object; (b) a first reset transistor for resetting the charge generating means; (c) a floating diffusion region receiving the charges from the charge generating means; and (d) a transfer transistor for receiving an address signal to transfer the charges from the charge generation means to the floating diffusion region; and a plurality of source following unit, each coupled to each column of unit pixel. And also, the present invention provides a driving method the CMOS image sensor.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: CMP (chemical/mechanical polishing) slurries that can rapidly remove a target layer and can effectively passivate a polishing stopper, with high selectivity. In one aspect, a CMP slurry comprises metal oxide abrasive particles, a removal rate accelerator, an anionic polymeric passivation agent having a molecular weight in a range of about 1,000 to about 100,000, a C1-C12 anionic passivation agent, and water.

Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

Abstract: Slurries for chemical mechanical polishing (CMP) are provided including a high planarity slurry and high selectivity ratio slurry. A high planarity slurry includes at least one kind of metal oxide abrasive particle and an anionic polymer passivation agent having a first concentration. A high selectivity ratio slurry includes at least one kind of the metal oxide abrasive particle, the passivation agent in a second concentration that is less than the first concentration of the passivation agent for the high planarity slurry, one of a quaternary amine and the salt thereof, and a pH control agent. The high selectivity ratio slurry has a pH in a range of about over an isoelectric point of a polishing target layer and less than an isoelectric point of a polishing stopper. In addition, a CMP method using the CMP slurries having high planarity and high selectivity ratio is provided.

Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.

Abstract: A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

Abstract: A chemical mechanical polishing slurry includes an additive of a quaternary ammonium compound having a form of {N—(R1R2R3R4)}+X−, in which R1, R2, R3, and R4 are radicals, and X− is an anion derivative including halogen elements. Preferably, the quaternary ammonium compound is one of [(CH3)3NCH2CH2OH]Cl, [(CH3)3NCH2CH2OH]l, [(CH3)3NCH2CH2OH]Br, [(CH3)3NCH2CH2OH]CO3, and mixtures thereof. The slurry may further include a pH control agent formed of a base such as KOH, NH4OH, and (CH3)4NOH, and an acid such as HCl, H2SO4, H3PO4, and HNO3. Also, the pH control agent can include [(CH3)3NCH2CH2OH]OH. The slurry may further include a surfactant such as cetyldimethyl ammonium bromide, cetyldimethyl ammonium bromide, polyethylene oxide, polyethylene alcohol or polyethylene glycol.

Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

Abstract: The present invention relates to a complementary metal-oxide-semiconductor (CMOS) image sensor, comprising: a plurality of unit pixel arrayed in rows and columns, wherein the unit pixel including: (a) a charge generating means for generating charges in response to lights reflected from an object; (b) a first reset transistor for resetting the charge generating means; (c) a floating diffusion region receiving the charges from the charge generating means; and (d) a transfer transistor for receiving an address signal to transfer the charges from the charge generation means to the floating diffusion region; and a plurality of source following unit, each coupled to each column of unit pixel. And also, the present invention provides a driving method the CMOS image sensor.

Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

Abstract: An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each unit pixel includes a light sensing element for sensing a light beam incident thereto and generating photoelectric charges, a transferring unit for transferring the photoelectric charges to a sensing node, a first resetting unit for making a fully depleted region within the light sensing element and resetting the sensing node by providing a power supply voltage to the sensing node, and a second resetting unit for transferring excess charges generated in the light sensing element to a power line when the sensing node is reset.

Abstract: A chemical mechanical polishing slurry includes an additive of a quaternary ammonium compound having a form of {N-(R1R2R3R4)}+X−, in which R1, R2, R3, and R4 are radicals, and X−is an anion derivative including halogen elements. Preferably, the quaternary ammonium compound is one of [(CH3)3NCH2CH2OH]Cl, [(CH3)3NCH2CH2OH]l, [(CH3)3NCH2CH20H]Br, [(CH3)3NCH2CH2H]CO3, and mixtures thereof. The slurry may further include a pH control agent formed of a base such as KOH, NH4OH, and (CH3)4NOH, and an acid such as HCI, H2SO4, H3PO4, and HNO3. Also, the pH control agent can include [(CH3)3NCH2CH2OH]OH. The slurry may further include a surfactant such as cetyldimethyl ammonium bromide, cetyldimethyl ammonium bromide, polyethylene oxide, polyethylene alcohol or polyethylene glycol.

Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.

Abstract: A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

Abstract: A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

Abstract: An analog semiconductor device capable of preventing open of interconnection lines and notching due to step between transistor and capacitor regions is disclosed. An analog semiconductor device according to the present invention, includes a semiconductor substrate; a first, a second, and a third isolating layer of trench type formed on the substrate and defining a transistor region and a capacitor region, respectively; a lower electrode of a capacitor formed in the surface of the substrate of the capacitor region; an oxide layer formed under the lower electrode and insulating the lower electrode and the substrate; an gate insulating layer formed on the substrate of the transistor region; an dielectric layer formed on the lower electrode; a gate formed on the gate insulating layer; an upper electrode of the capacitor formed on the dielectric layer.