Abstract: A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed.

Abstract: An integrated circuit device is manufactured by forming a pattern on a substrate. The pattern may include two or more mesa regions. The pattern and the substrate are coated with a spin on glass layer and then the spin on glass layer is dissolved so that the spin on glass layer is recessed from upper surfaces of the mesa regions opposite the substrate. Before dissolving the spin on glass layer, a thermal treatment may be applied to remove a solvent from the spin on glass layer.

Abstract: A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

Abstract: An integrated circuit device is manufactured by forming a pattern on a substrate. The pattern may include two or more mesa regions. The pattern and the substrate are coated with a spin on glass layer and then the spin on glass layer is dissolved so that the spin on glass layer is recessed from upper surfaces of the mesa regions opposite the substrate. Before dissolving the spin on glass layer, a thermal treatment may be applied to remove a solvent from the spin on glass layer.

Abstract: Disclosed is a semiconductor device capable of reducing parasitic capacitance and a method thereof, the method including the steps of depositing sequentially an inorganic silicon oxide layer and a low dielectric constant organic silicon oxide layer on a substrate, forming a partial trench with a predetermined depth in the organic silicon oxide layer by patterning, oxygenating an inner wall of the partial trench, and forming a trench by etching the partial trench with hydrofluoric acid (HF).

Abstract: Disclosed is a method for forming interconnection lines using a hydrosilsesquioxane (HSQ) layer as an interlayer insulating layer. A HSQ layer is formed over a semiconductor substrate and an entire surface of the HSQ layer is subjected to plasma treatment. It is then possible to pattern the HSQ layer using photo etching, for the bond structure density of an upper part of the HSQ layer has been increased due to the plasma treatment. An opening is formed by patterning the treated HSQ layer and then a conductive layer filling the opening is formed. In this manner, a multilayer interconnection structure can be formed with a low dielectric layer made of HSQ, thereby reducing the resistance-capacitance (RC) delay.

Abstract: A .beta.-methylcarbapenem compound of formula (I), a salt or an ester thereof, a process for the preparation thereof and a anti-bacterial composition containing same: ##STR1## wherein: R.sup.1 is a C.sub.1-6 alkyl, C.sub.2-6 alkenyl, cycloalkyl, aryl or heterocyclic aryl group.

Abstract: Recording of a weekly serial TV program which is broadcast at least two times or more a week at designated times in a video cassette recorder having a system controller, wherein the system controller is provided with a memory and a timer for expressing a current time, a current day of the week and a current day/month, is carried out by way of: (a) setting at the memory a recording start date and a recording end date to fix the overall term of recording the weekly serial TV program; two or more days of the week on which the weekly serial TV program is broadcast; a recording start time and a recording end time to designate the duration of recording each segment of the weekly serial TV program; (b) comparing the current day/month with the recording start day/month set at the memory to determine if the current day/month has reached the recording start day/month; (c) comparing the current day of the week with each of the two or more days of the week set at the memory to determine if the current day of the week has