Abstract: A semiconductor integrated circuit device may include a first circuit, a second circuit, and a delay circuit. The first circuit may include an output node. The second circuit may include an output node. The delay circuit may be coupled between the output node of the first circuit and the output node of the second circuit to selectively delay an output signal from the first circuit and an output signal from the second circuit.

Abstract: A semiconductor apparatus may include a column select signal generation circuit and a control signal generation circuit. The column select signal generation circuit may generate a column select signal by driving an output node of the column select signal with a first drivability in response to a column decoding signal and adjust the first drivability according to a drivability control signal. The control signal generation circuit may generate the drivability control signal according to a row decoding signal.

Abstract: A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

Abstract: A semiconductor integrated circuit device may include a first circuit, a second circuit, and a delay circuit. The first circuit may include an output node. The second circuit may include an output node. The delay circuit may be coupled between the output node of the first circuit and the output node of the second circuit to selectively delay an output signal from the first circuit and an output signal from the second circuit.

Abstract: A semiconductor device may be provided. The semiconductor device may include a pre-charge pulse signal generation circuit configured to generate a pre-charge pulse signal based on the period control signal and a word line off signal. The enablement of the pre-charge pulse signal may be delayed based on the enablement of the word line off signal.

Abstract: A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a second block control signal in response to a refresh pulse signal, a second refresh control block for generating a first refresh control pulse signal and a second refresh control pulse signal corresponding to a first refresh operation section of the first memory block and a second refresh operation section of the second memory block, respectively, in response to the refresh pulse signal and the first and second block control signals, and a third refresh control block for controlling the first and second memory blocks so that a first refresh operation of the first memory block and a second refresh operation of the second memory block are discontinuously performed in response to the first and second refresh control pulse signals.

Abstract: A semiconductor device includes a first memory block, a second memory block, a first refresh control block for generating a first block control signal and a second block control signal in response to a refresh pulse signal, a second refresh control block for generating a first refresh control pulse signal and a second refresh control pulse signal corresponding to a first refresh operation section of the first memory block and a second refresh operation section of the second memory block, respectively, in response to the refresh pulse signal and the first and second block control signals, and a third refresh control block for controlling the first and second memory blocks so that a first refresh operation of the first memory block and a second refresh operation of the second memory block are discontinuously performed in response to the first and second refresh control pulse signals.

Abstract: A semiconductor device includes: a plurality of internal circuits which receive commands through a plurality of independent command lines in a first operation mode and receive a common command through a common command line in a second operation mode; and an operation control block which duplicates a command applied through a representative independent command line, which is selected among the plurality of independent command lines, in the second operation mode and transmits the duplicated command as the common command to the common command line.

Abstract: A semiconductor memory apparatus may include a refresh counting portion configured to count the number of times a refresh signal is received by the refresh counting portion, and configured to generate a smart refresh enable signal when the number of times the refresh signal is received by the refresh counting portion reaches a predetermined number and an address arithmetic portion configured to latch an address, and, when the smart refresh enable signal is enabled, configured to perform an arithmetic operation of addition and subtraction on the latched address and output a result of the arithmetic operation as an arithmetic address. The semiconductor memory apparatus may also include an address selection portion configured to output one of the arithmetic addresses and one of the addresses as a selection address in response to the smart refresh enable signal.

Abstract: A refrigerator includes storage chambers storing foods, cooling devices cooling the storage chambers, a display unit displaying a picture to manage foods, a communication unit receiving product information of products purchased by a user from a seller server, and a control unit extracting product information of food items purchased by the user from the product information of the products and controlling the display unit so as to display food management information generated based on the extracted product information of the food items. The refrigerator may display management information of the food items purchased by the user without separate input of the product information of the food items purchased by the user.

Abstract: A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.

Abstract: A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state.

Abstract: A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address.

Abstract: A semiconductor IC device which includes a common column signal generating block and a column strobe signal generating block. The common signal generating block can provide precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses. The column strobe signal generating block can provide a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.

Abstract: A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response to a column command signal and a row address strobe pulse generator for receiving an active command signal or the column command signal to produce a row address strobe pulse in response to a test mode signal.

Abstract: The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.

Abstract: A semiconductor IC device includes a common column signal generating block providing precolumn strobe signals by using external command signals and a first group of bank addresses among a plurality of bank addresses, and a column strobe signal generating block providing a plurality of column strobe signals to selectively activate a plurality of banks by using the precolumn strobe signals and a second group of bank addresses among the plurality of bank addresses that are not used when the precolumn strobe signals are generated.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state.

Abstract: A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response to a column command signal and a row address strobe pulse generator for receiving an active command signal or the column command signal to produce a row address strobe pulse in response to a test mode signal.