Abstract: The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks grouped into a first group and a second group; and a bank control unit for selecting one of the first group and the second group in response to a bank address to transfer an address to the selected group.

Abstract: A data input circuit of a semiconductor memory device and a data input operating method thereof, in which data input margin can be secured.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: A data input circuit of a semiconductor memory device and a data input operating method thereof, in which data input margin can be secured.

Abstract: Provided is directed to a data input apparatus and a method of DDR SDRAM which can improve reliability of a circuit operation by transferring data inputted after applying a data strobe signal DQS to an input/output bus GIO by a exact timing, by means of correctly arranging the data strobe signal DQS and a data input strobe pulse dinstbp regardless of time difference of inputting the data strobe signal DQS after a write command, in response to generating a data input strobe pulse dinstbp used to load data to the input/output bus GIO as a data strobe pulse dsp identical to the data strobe signal DQS.

Abstract: The integrated circuit teat system and method prevent the occurrence of frost under a very low temperature environment during the exchange of integrated circuits under environmental testing and allows for the continuous testing thereof. The integrated circuit test system comprises a test chamber, a portion of which is adapted to interface with a tester having a circuit panel. An auxiliary chamber is adjacent the test chamber, the auxiliary chamber including a first door between the auxiliary chamber and the test chamber, the auxiliary chamber further including a second door between the auxiliary chamber and an external region, the auxiliary chamber for receiving a sample prior to and following a test. A transfer unit is also in the chamber, for transferring the sample between the test chamber and the auxiliary chamber through the first door. Accordingly, the time consumed during the exchange of testing samples is shortened.

Abstract: The integrated circuit test system and method prevent the occurrence of frost under a very low temperature environment during the exchange of integrated circuits under environmental testing and allows for the continuous testing thereof. The integrated circuit test system comprises a test chamber, a portion of which is adapted to interface with a tester having a circuit panel. An auxiliary chamber is adjacent the test chamber, the auxiliary chamber including a first door between the auxiliary chamber and the test chamber, the auxiliary chamber further including a second door between the auxiliary chamber and an external region, the auxiliary chamber for receiving a sample prior to and following a test. A transfer unit is also in the chamber, for transferring the sample between the test chamber and the auxiliary chamber through the first door. Accordingly, the time consumed during the exchange of testing samples is shortened.