Abstract: A semiconductor device according to embodiments may include an interposer, a plurality of devices stacked on the interposer, a cooling device provided in at least one of the devices and including a passage for a cooling material, and a connection electrode provided between the devices, in which the connection electrode connects a signal electrode in an upper device to a signal electrode in a lower device.

Abstract: Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor.

Abstract: A semiconductor device and a fabricating method thereof are provided. A PMD layer and at least one IMD layer are formed on a semiconductor substrate. A through-electrode penetrates through the PMD layer and the IMD layer, and a connecting electrode connects to the through-electrode.

Abstract: Rapid thermal processing apparatus methods are disclosed. In a disclosed apparatus, rapid thermal processing is carried out when the residual oxygen detected by a residual oxygen detector does not exceed a predetermined tolerance level. Accordingly, it is possible to prevent the contact resistance of the wafers from increasing due to the presence of excessive oxygen.

Abstract: An image sensor according to embodiments may include a first substrate having photodiode cells, a second substrate having a logic circuit, and connection electrodes that may electrically connect the photodiode cells with the logic circuit. In embodiments, more area may be available on the first substrate for photodiode cells and light loss may be reduced.

Abstract: A method for manufacturing an inductor using a system-in-package (SIP) includes forming a first penetration electrode in a silicon substrate; depositing an insulating film on a first surface of the silicon substrate, and patterning the insulating film to form an inductor hole and a second penetration hole aligned with the first penetration hole; forming an inductor in the inductor hole and a second penetration electrode in the second penetration hole; and depositing a protective film on the insulating film and performing a back grind process such that the first penetration electrode is exposed from a second surface of the silicon substrate, the second surface being opposed to the first surface.

Abstract: Disclosed is checking a drive state of a backlight lamp of a liquid crystal display device and notifying to an external entity whether it is normally driven in which level or is difficult to be normally driven.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.

Abstract: A sputtering apparatus for forming a low-resistance uniform metal silicide layer without additional heat treatment and a metal silicide layer forming method using the same are provided. The sputtering apparatus includes a sputtering chamber; a gas introduction port formed at an upper location of a lateral wall of the sputtering chamber; a gas exhaust port formed at a bottom wall of the sputtering chamber; a target located in an upper region of the sputtering chamber; a power source to supply the target with high-frequency electric power; a stage located in a bottom region of the sputtering chamber to heat the semiconductor substrate; and a sieve provided between the target and the semiconductor substrate to improve straightness of charged metal particles.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: A method for fabricating copper wiring of a semiconductor device comprises forming a deposition stop time detection pattern having two trench structures positioned with a predetermined distance from each other on a dielectric substrate; positioning a deposition stop time detection apparatus having a plurality of detection electrodes and a guide device above the deposition stop time detection pattern; depositing copper on the substrate; and stopping deposition of the copper by an electric signal being generated when the two detection electrodes are electrically connected by the copper deposited in the two trench structure.

Abstract: A method of forming an aluminum line of a semiconductor device where first A metal thin layer, a first aluminum layer, and a first B metal thin layer are sequentially applied on an interlayer insulating layer. A photolithography process is performed to form a metal line pattern, and etching is performed thereon. An intermetallic dielectric layer is applied on the metal line pattern. The first B metal thin layer is removed by a chemical mechanical planarization process to form a first stage metal line. A second aluminum layer and a second metal thin layer are sequentially applied. Photoresist is applied, a photolithography process is performed to form a metal line pattern, and etching is performed to form a second stage metal line. An intermetallic dielectric layer is applied on the second stage metal line. A chemical mechanical planarization process is performed on the second intermetallic dielectric layer.

Abstract: The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.

Abstract: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.

Abstract: A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein the interlayer insulating film is provided with holes having a designated shape; a barrier metal layer, a copper seed layer, and a copper layer sequentially formed in the holes of the interlayer insulating film; and a capping layer formed between the interlayer insulating film and the second insulating layer. The capping layer formed between the interlayer insulating film and the second insulating layer may be made of a negatively charged insulating material, thereby improving electro-migration characteristics at an interface between the capping layer and the copper layers.

Abstract: A semiconductor device and fabricating method thereof are provided. A semiconductor substrate includes at least two holes for receiving devices, and at least two devices are inserted into the holes of the semiconductor substrate. Connection electrodes electrically connect the devices with each other, and the bonding pad portion provides signal connection between the connected devices and an outside device.

Abstract: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a logic circuit part. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the logic circuit part of the second wafer.

Abstract: A semiconductor device including an integrated device having a first device having a first pad part formed on a top metal layer, a second device arranged at the circumference of the first device and having a second pad part formed on the top metal layer, a connecting electrode electrically connecting the first pad part to the second pad part; and a bonding pad part connected the integrated device and connecting signals to the external.

Abstract: A semiconductor device and a fabricating method thereof are provided. A first device having a photodiode cell can be disposed adjacent to a second device having a transistor, and a connection electrode can electrically connect the first device and the second device.