Abstract: A NAND-type nonvolatile memory device includes a first string and a second string. The ends of each of the first and second strings are connected to a common bit line and a common source line, respectively. Each of the first string and the second string have a string selection transistors, a plurality of unit devices and a source selection transistor. Word lines are respectively connected to control gates of the unit devices in the same rows. A first string selection line and a second string selection line are respectively connected to the gates of the string selection transistors of the first string and the second string. A first source selection line and a second source selection line are respectively connected to the gates of the first string and the second string.

Abstract: There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.

Abstract: Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.

Abstract: Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner.

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract: A non-volatile memory device with improved integration and/or improved performance by reducing an area per bit and controlling a body bias, and a method of fabricating the same. The non-volatile memory device may use surface portions of the outer side surfaces and/or the upper surfaces of at least one pair of fins protruding from a body and extending, spaced from each other along one direction, as at least one pair of channel regions. At least one control gate electrode may be formed across the channel regions, and at least one pair of storage nodes may be interposed in at least one portion between the control gate electrode and the channel regions.

Abstract: A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.

Abstract: A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.

Abstract: A fin FET CMOS device, a method of manufacturing the same, and a memory including the fin FET CMOS device are provided. The CMOS device may include a substrate, an n-type transistor disposed on the substrate, an interlayer insulating layer disposed on the n-type transistor, and a p-type transistor disposed on the interlayer insulating layer. The n-type transistor and the p-type transistor may have a common gate insulating layer and a fin gate.

Abstract: Provided is a memory device comprising a molecular adsorption layer. The memory device includes: a substrate; a source electrode and a drain electrode formed on the substrate and separated from each other; a carbon nanotube (CNT) layer electrically connected to the source electrode and the drain electrode; a memory cell contacting the CNT so as to store a charge from the CNT; and a gate electrode formed on the memory cell, wherein the memory cell comprises: a first insulating layer formed on the CNT; a molecular adsorption layer which is formed on the first insulating layer and acts as a charge storage layer; and a second insulating layer formed on the molecular adsorption layer.