Abstract: A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR).

Abstract: The present invention relates to a time digital converter, and more particularly, to a noise-shaping time to digital converter (TDC) that has a 1-bit output and uses a delta-sigma modulation method. The noise-shaping time to digital converter (TDC) that has the 1-bit output and uses the delta-sigma modulation method in accordance with the present invention eliminates the need for a large number of D flip-flops or counters and a plurality of delay units connected in series to one another because the time to digital converter is fabricated such that a delay element has a resolution of the effective delay time in a semiconductor process, unlike the conventional time to digital converter. Therefore, the time to digital converter of the present invention has an advantage in that an extremely high resolution and high linearity can be achieved with an efficient circuit configuration and low power consumption.

Abstract: The present invention relates to a time digital converter, and more particularly, to a noise-shaping time to digital converter (TDC) that has a 1-bit output and uses a delta-sigma modulation method. The noise-shaping time to digital converter (TDC) that has the 1-bit output and uses the delta-sigma modulation method in accordance with the present invention eliminates the need for a large number of D flip-flops or counters and a plurality of delay units connected in series to one another because the time to digital converter is fabricated such that a delay element has a resolution of the effective delay time in a semiconductor process, unlike the conventional time to digital converter. Therefore, the time to digital converter of the present invention has an advantage in that an extremely high resolution and high linearity can be achieved with an efficient circuit configuration and low power consumption.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: An apparatus and a method for transmitting and receiving a spike event in a neuromorphic chip. A transmission apparatus of the neuromorphic chip outputs addresses sequentially and repeatedly to an address bus, and when a spike generated by a neuron is detected by the transmission apparatus, outputs a strobe at a first time when one of the addresses being output sequentially and repeatedly becomes identical to an address of the neuron that generated the spike. A receiving apparatus of the neuromorphic chip inputs an address through the address bus at a strobe detection time when the strobe is detected by the receiving apparatus.

Abstract: A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference ?t, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time ?, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract: A time-domain voltage comparator for an analog-to-digital converter includes a first voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; a second voltage-to-time converter configured to be connected in series with at least one time delay cell and convert an input voltage into time information; and a phase comparator configured to determine a difference between times outputted from the first voltage-to-time converter and the second voltage-to-time converter.

Abstract: Provided is a portable power supply apparatus for generating microwave plasma, capable of minimizing a power reflected from a plasma generation apparatus and improving power consumption of the plasma generation apparatus by generating the plasma by using a microwave having a specific frequency, monitoring the power reflected from the plasma generation apparatus after the generation of the plasma, detecting a changed impedance matching condition, and correcting the frequency.

Abstract: Provided is a coagulation apparatus using cold plasma. In the coagulation apparatus, the cold plasma is generated by a microwave resonator with low power consumption in the atmosphere, and the cold plasma is vented on a bleeding portion of a wound. Accordingly, it is possible to accelerate coagulation process, to reduce unfavorable side effect such as burns on the wound, and to efficiently sterilize the wound, simultaneously. In addition, it is possible to implement a small-sized portable coagulation apparatus.

Abstract: Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a capacitive coupling between adjacent signal lines is smaller than an inductive coupling therebetween, so that far-end crosstalk occurs. According to the present invention, the capacitive coupling between the adjacent signal lines is increased to reduce the far-end crosstalk. A vertical-stub type microstrip transmission line is provided.

Abstract: A time-to-digital converter includes a phase-difference enhancement section configured to receive first and second input signals having a reference phase difference ?t, and to output first and second output signals having an enhanced phase difference; and a comparison section configured to receive the first and second output signals, to compare a phase difference between the first and second output signals with a reference delay time ?, and to output a comparison signal. The time-to-digital converter has a high resolution. That is to say, the time-to-digital converter has a resolution less than the minimum phase delay time of a delay element, which is obtainable in a corresponding semiconductor process.

Abstract: Provided is a microstrip transmission line for reducing far-end crosstalk. In a conventional microstrip transmission line on a printed circuit board, a capacitive coupling between adjacent signal lines is smaller than an inductive coupling therebetween, so that far-end crosstalk occurs. According to the present invention, the capacitive coupling between the adjacent signal lines is increased to reduce the far-end crosstalk. A vertical-stub type microstrip transmission line is provided.

Abstract: Provided is a portable power supply apparatus for generating microwave plasma, capable of minimizing a power reflected from a plasma generation apparatus and improving power consumption of the plasma generation apparatus by generating the plasma by using a microwave having a specific frequency, monitoring the power reflected from the plasma generation apparatus after the generation of the plasma, detecting a changed impedance matching condition, and correcting the frequency.

Abstract: Provided is a coagulation apparatus using cold plasma. In the coagulation apparatus, the cold plasma is generated by a microwave resonator with low power consumption in the atmosphere, and the cold plasma is vented on a bleeding portion of a wound. Accordingly, it is possible to accelerate coagulation process, to reduce unfavorable side effect such as burns on the wound, and to efficiently sterilize the wound, simultaneously. In addition, it is possible to implement a small-sized portable coagulation apparatus.

Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Abstract: Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair.