Abstract: Disclosed is a semiconductor memory device which includes an offset-compensated amplifier circuit. The offset-compensated amplifier circuit enables a flip-flop sense amplifier to perform a stable sensing operation irrespective of its own offset voltage. A part of the offset-compensated amplifier circuit is located in a first region (for example, a region that includes the flip-flop sense amplifier), and the other thereof is located in a second region (for example, a region where drivers related to the flip-flop sense amplifier are located). With this distributed arrangement structure, an offset-compensated amplifier circuit can be obtained n the semiconductor memory device.

Abstract: In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Abstract: A plurality of internal circuits of a memory device are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives a first power supply voltage, and a second power port of the memory device receives a second power supply voltage, where the first power supply voltage is less than the second power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the second power supply voltage.

Abstract: A voltage booster circuit includes first and second capacitors and a switch circuit coupled to the first and second capacitors and operative to apply a power supply across the first and second capacitors in series responsive to a first signal to thereby charge the first and second capacitors and to couple the first and second capacitors in parallel between an output terminal and a power supply node of the power supply responsive to deassertion of the first signal and assertion of a second signal to thereby boost a voltage at the output terminal. The first and second signals may be alternately asserted in a succession of time periods, e.g., the first and second signals may be asserted in respective non-overlapping time periods.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Abstract: A semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each one of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the corresponding sub word line to the corresponding main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line. The sub word line drivers can include a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line. A second transistor is configured to connect the main word line to the sub word line in response to an activation of the sub word line selection signal. A third transistor is configured to connect the main word line to a gate of the first transistor in response to a high voltage.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Abstract: A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

Abstract: A semiconductor memory device for performing an effective data sensing operation with a simple constitution. The device comprises first and second blocks each disposed about a sense amplifier and formed of a plurality of bitlines; a circuit for connecting a bitline coupled to memory cell of the first block and a complementary bitline of the second block to the sense amplifier, and charging a bitline coupled to memory cell of the second block and a complementary bitline of the first block up to a predetermined voltage, in response to a signal.

Abstract: An integrated circuit device includes a pair of bit lines and a pair of sense amplifiers respectively coupled to the pair of bit lines. A sense amplifier driver is coupled to one of the pair of sense amplifiers and is disposed between the pair of sense amplifiers. In other embodiments, an integrated circuit device includes a plurality of sense amplifier pairs including a first group of sense amplifiers and a second group of sense amplifiers. A first plurality of sense amplifier drivers is coupled to the first group of sense amplifiers such that a ratio of the first group of sense amplifiers to the first plurality of sense amplifiers drivers is at least 2:1. A second plurality of sense amplifier drivers is coupled to the second group of sense amplifiers such that a ratio of the second group of sense amplifiers to the second plurality of sense amplifier drivers is at least 2:1.

Abstract: A voltage detecting circuit includes first and second reference voltage generating circuits. The first reference voltage generating circuit provides a reference voltage during a normal operation mode. The second reference voltage generating circuit provides a reference voltage during a test mode. A comparison voltage generating circuit is also included and provides a comparison voltage during both modes in response to a boosted voltage. A differential amplifier circuit is further included in the voltage detecting circuit. The differential amplifier generates an amplified difference signal that is used to generate a voltage level detection signal. The voltage level detection signal controls a pumping operation for generating the boosted voltage level. A bypass circuit may also be provided to lower a detected boosted voltage level and allow operation at lower voltage levels.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: An input/output sense amplifier circuit of a semiconductor memory device is disclosed which comprises a current sense amplifier, a voltage sense amplifier and a latch circuit. The latch circuit includes a first differential amplifier for receiving the differential signals from the voltage sense amplifier; a second differential amplifier for receiving the differential signals from the voltage sense amplifier; and a gain varying circuit coupled between output terminals of the first and second differential amplifiers and setting a voltage gain of each of the first and second differential amplifiers that varies in response to the latch signal. By this configuration, a time normally required to be provided to the latch signal is obviated, thus reducing lead time of the memory device.

Abstract: A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

Abstract: Disclosed is a semiconductor memory device performing an effective data sensing operation with a simple constitution. The device comprises first and second blocks each disposed about a sense amplifier and formed of a plurality of bitlines; a circuit for connecting a bitline coupled to memory cell of the first block and a complementary bitline of the second block to the sense amplifier, and charging a bitline coupled to memory cell of the second block and a complementary bitline of the first block up to a predetermined voltage, in response to a signal.

Abstract: A semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each one of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the corresponding sub word line to the corresponding main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line. The sub word line drivers can include a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line. A second transistor is configured to connect the main word line to the sub word line in response to an activation of the sub word line selection signal. A third transistor is configured to connect the main word line to a gate of the first transistor in response to a high voltage.

Abstract: An input buffer circuit consumes a small amount of power and operates rapidly. The input buffer circuit includes a differential amplifier, a buffer, and a switched current path connected to the differential amplifier. The differential amplifier receives an input signal and a reference voltage and generates an internal signal from a node in the differential amplifier. The buffer generates an output signal from the internal signal. The switched current path can include a current source and/or a current sink that includes series connected transistors with gates that respectively receive the input and output signals. The switched current path is temporarily activated to provide a current that reduces charging or discharging time of the node in the amplifier. The current thus reduces the delay time between edges in the input signal and corresponding edges in the output signal. Accordingly, the input buffer circuit operates rapidly.