Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate an error-reduced version of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate an error-reduced version of encoded data for an error correction coding (ECC) decoder, e.g., to facilitate decoding of the error-reduced version of encoded data at the decoder. In this manner, neural networks or recurrent neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by reducing errors present in encoded data due to storage or transmission.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks to estimate message probability compute data based on encoded data (e.g., data encoded using one or more encoding techniques). The neural networks and/or recurrent neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing a neural network or recurrent neural network to estimate message probability compute data for a message probability compute (MPC) decoder. In this manner, neural networks or recurrent neural networks described herein may be used to implement aspects of error correction coding (ECC) decoders, e.g., an MPC decoder that iteratively decodes encoded data.

Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured with: a Central Processing Unit, a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of an application executable by the Central Processing Unit; one or connections among the random access memory, the Deep Learning Accelerator and the Central Processing Unit; and an input/output interface to an external peripheral bus. While the Deep Learning Accelerator is executing the first instructions to convert sensor data according to the Artificial Neural Network to inference results, the Central Processing Unit may execute the application that uses inference results from the Artificial Neural Network.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.

Abstract: Examples described herein utilize multi-layer neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The multi-layer neural networks include an encoder configured to encode input data using encoded bits in accordance with an encoding technique and to provide encoded input data, and a memory configured to receive the encoded input data from the encoder and configured to store the encoded input data. The multi-layer neural networks further include combiners configured to receive the encoded input data from the memory and further configured to combine the encoded input data among a set of predetermined weights. The combiners are further configured to provide encoded data with reduced noise, the noise introduced by the memory.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Abstract: Examples described herein include apparatuses and methods to perform adaptive spatial diversity in a MIMO system. An example apparatus may include a plurality of receiving antennas and a wireless receiver configured to receive a respective plurality of receive signals each from a respective receiving antenna of the plurality of receiving antennas. The wireless signal may be further configured to apply a corresponding weight to each of the plurality of signals to provide a plurality of weighted signals and to apply an eigenfilter to the plurality of weighted signals provide a transfer function. The wireless receiver further configured to perform a fast Fourier transform (FFT) on the transfer function to provide output signals in the frequency domain.

Abstract: Examples described herein include apparatuses and methods for full duplex device-to-device cooperative communication. Example systems described herein may include self-interference noise calculators. The output of a self-interference noise calculator may be used to compensate for the interference experienced due to signals transmitted by another antenna of the same wireless device or system. In implementing such a self-interference noise calculator, a selected wireless relaying device or wireless destination device may operate in a full-duplex mode, such that relayed messages may be transmitted as well as information from other sources or destinations during a common time period (e.g., symbol, slot, subframe, etc.).

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can convert a description of an artificial neural network into a generic result of compilation according to a specification of a generic Deep Learning Accelerator and then map the first result of compilation into a platform-specific result according to a specification of a specific hardware platform of Deep Learning Accelerators. The platform-specific result can be stored into the RAM of the integrated circuit device to enable the integrated circuit device to autonomously perform the computation of the artificial neural network in generating an output in response to an input to the artificial neural network.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A compiler can convert a description of an artificial neural network into a compiler output through optimization and/or selection of hardware options of the integrated circuit device. The compiler output can include parameters of the artificial neural network, instructions executable by processing units of the Deep Learning Accelerator to generate an output of the artificial neural network responsive to an input to the artificial neural network, and hardware options to be stored in registers connected to control hardware configurations of the processing units.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler can identify a plurality of portions of an artificial neural network for implementation on a plurality of such integrated circuit devices respectively. The compiler converts a description of the artificial neural network into a plurality of compiler outputs executable on the plurality of devices to generate an output of the artificial neural network response to an input to the artificial neural network. Intermediate results are communicated among the devices in generating the output of the artificial neural network.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system may allocate the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first narrowband Internet of Things (IoT) transmission and a second narrowband IoT transmission. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first narrowband IoT transmission and symbols indicative of the second narrowband IoT transmission. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second narrowband IoT transmission.