Patents by Inventor James B. Keller
James B. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6694424Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC.Type: GrantFiled: January 3, 2000Date of Patent: February 17, 2004Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad
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Publication number: 20040024945Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.Type: ApplicationFiled: July 29, 2003Publication date: February 5, 2004Applicant: Broadcom CorporationInventors: James B. Keller, Chun H. Ning, Kwong-Tak A. Chui, Mark D. Hayter
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Publication number: 20040024836Abstract: A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data).Type: ApplicationFiled: July 28, 2003Publication date: February 5, 2004Applicant: Advanced Micro Devices, Inc.Inventors: James B. Keller, Dale E. Gulick
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Patent number: 6687789Abstract: A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined.Type: GrantFiled: January 3, 2000Date of Patent: February 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Keith R. Schakel, Puneet Sharma
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Publication number: 20030217233Abstract: A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.Type: ApplicationFiled: October 11, 2002Publication date: November 20, 2003Applicant: Broadcom Corp.Inventors: Joseph B. Rowlands, James B. Keller
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Patent number: 6651144Abstract: A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state.Type: GrantFiled: June 18, 1998Date of Patent: November 18, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Rahul Razdan, James B. Keller, Richard E. Kessler
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Patent number: 6651161Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC.Type: GrantFiled: January 3, 2000Date of Patent: November 18, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad
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Patent number: 6647490Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Additionally, each entry may include a link to another entry storing instruction pointers to the next instructions within the predicted instruction stream, and a next fetch address corresponding to the first instruction within the next entry. The next fetch address may be provided to the instruction cache to fetch the corresponding instruction bytes.Type: GrantFiled: October 14, 1999Date of Patent: November 11, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Puneet Sharma, Keith R. Schakel, Francis M. Matus
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Patent number: 6636959Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.Type: GrantFiled: October 14, 1999Date of Patent: October 21, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Puneet Sharma, Keith R. Schakel, Francis M. Matus
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Patent number: 6633936Abstract: An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected.Type: GrantFiled: September 26, 2000Date of Patent: October 14, 2003Assignee: Broadcom CorporationInventors: James B. Keller, Chun H. Ning, Kwong-Tak A. Chui, Mark D. Hayter
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Patent number: 6631401Abstract: A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data).Type: GrantFiled: December 21, 1998Date of Patent: October 7, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Dale E. Gulick
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Publication number: 20030182543Abstract: A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Additionally, each entry may include a link to another entry storing instruction pointers to the next instructions within the predicted instruction stream, and a next fetch address corresponding to the first instruction within the next entry. The next fetch address may be provided to the instruction cache to fetch the corresponding instruction bytes.Type: ApplicationFiled: October 14, 1999Publication date: September 25, 2003Inventors: JAMES B. KELLER, PUNEET SHARMA, KEITH R. SCHAKEL, FRANCIS M. MATUS
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Patent number: 6625685Abstract: A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations.Type: GrantFiled: September 20, 2000Date of Patent: September 23, 2003Assignee: Broadcom CorporationInventors: James Y. Cho, James B. Keller, Mark D. Hayter
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Patent number: 6622237Abstract: A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC.Type: GrantFiled: January 3, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad, Keith R. Schakel
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Patent number: 6622235Abstract: A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation.Type: GrantFiled: January 3, 2000Date of Patent: September 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Ramsey W. Haddad, Stephan G. Meier
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Publication number: 20030105985Abstract: A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer.Type: ApplicationFiled: January 11, 2002Publication date: June 5, 2003Inventors: James B. Keller, Daniel W. Dobberpuhl
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Publication number: 20030097416Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.Type: ApplicationFiled: October 11, 2002Publication date: May 22, 2003Applicant: Broadcom Corp.Inventors: Barton J. Sano, Joseph B. Rowlands, James B. Keller, Laurent R. Moll, Koray Oner, Manu Gulati
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Publication number: 20030095557Abstract: A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel.Type: ApplicationFiled: September 17, 1999Publication date: May 22, 2003Inventors: JAMES B. KELLER, DERRICK R. MEYER
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Publication number: 20030093304Abstract: A method for evaluating and managing short term risk includes the steps of identifying a population of risks, assigning baseline factors to risks in the population, developing, by a statistical regression technique, a table of modification factors, modifying the baseline factors assigned to the risk and generating one or more quotes for insurance coverage using the modified factors. A system with which the method may be practiced includes first and second computers, and programs to allow a user of the second computer to generate one or more quotes on the first computer for review and consideration. The system and method allow for more precise and rigorous analysis and underwriting of certain short term risks.Type: ApplicationFiled: October 28, 2002Publication date: May 15, 2003Inventors: James B. Keller, Karen J. Edgerton
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Patent number: 6564315Abstract: A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued.Type: GrantFiled: January 3, 2000Date of Patent: May 13, 2003Assignee: Advanced Micro Devices, Inc.Inventors: James B. Keller, Ramsey W. Haddad, Stephan G. Meier