Abstract: The invention is directed to a method and circuit for performing an addition operation in successive pipelined instructions which utilize a sliced ALU. Successive microinstructions are monitored to determine if both microinstructions are add operations. Further, it is determined whether the use of the destination of the first microinstruction is a source for the add operation in the second microinstruction. If both microinstructions are add operations and the destination of the first microinstruction is used as the source for the second microinstruction and one of the addends of the second microinstruction is a small addend then the circuit detects whether a carry-out occurred in the least significant slice of the second instruction. If there is no carry-out, the result for the more significant slice of the second microinstruction answer. However, if a carry-out was detected, then the result for the second microinstruction's more significant slice is the sum+1 of the second microinstruction.

Abstract: In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

Abstract: A cache memory unit is disclosed in which, in response to the application of a write command, the write operation is performed in two system clock cycles. During the first clock cycle, the data signal group is stored in a temporary storage unit while a determination is made if the address signal group associated with the data signal group is present in the cache memory unit. When the address signal group is present, the data signal group is stored in the cache memory unit during the next application of a write command to the cache memory unit. If a read command is applied to the cache memory unit involving the data signal group stored in the temporary storage unit, then this data signal group is transferred to the central processing unit in response to the read command. Instead of performing the storage into the cache memory unit as a result of the next write command, the storage of the data signal in the cache memory unit can occur during any free cycle.