Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract: A phased locked loop (PLL) incorporates multiple voltage controlled oscillators including one that operates in a lower frequency range than an operational VCO used by the PLL. A VCO selection circuit allows the system to select from one or more alternate VCOs. A ring oscillator VCO may be used as the alternate VCO for a PLL that uses a LC VCO for the operational VCO. While the ring oscillator VCO provides lower performance, the ring oscillator VCO allows the system with the PLL to be run at a lower speed for testing, debugging or characterization.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract: A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current minors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Abstract: A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.

Abstract: A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.

Abstract: A circuit for implementing a control voltage mirror is provided. A filter includes a filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier having a positive input connected to the control voltage, and a negative input is connected to an output and coupled to the distal side of the capacitor. Voltage across the capacitor is held to be near or at zero volts, substantially eliminating capacitor leakage current.

Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Abstract: A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Abstract: A semiconductor chip having a P? substrate and an N+ epitaxial layer grown on the P? substrate is shown. A P? circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Abstract: A system is disclosed, which may include a differential charge pump. The differential charge pump may include a first and a second H-bridge circuit, each driving, on a respective output, an output current that is substantially similar over an output voltage operating range. The differential charge pump may be designed to receive increment, decrement and bias signals, and drive, in response to the increment and decrement signals, the output current to draw each H-bridge circuit output towards a first or a second supply voltage. The differential charge pump may also be designed to increase, in response to the bias signals, the output voltage operating range over which the output current is substantially similar. The differential charge pump may also include a bias signal generator, designed to generate bias signals in response to H-bridge circuit output voltages.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.