Abstract: A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.

Abstract: A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

Abstract: A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization.

Abstract: A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

Abstract: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

Abstract: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

Abstract: A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO.

Abstract: A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.

Abstract: A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical hierarchical design applications, by assigning, from a schematic of the integrated circuit, a viewable scope of a block element desired for traversing. Opening the viewable scope of the block element, by using a mouse scrolling device to cause a cursor to highlight and roll in a downward direction over the highlighted block element, while holding down a predefined keyboard key. Then closing the viewable scope of the block element, by causing the cursor to be positioned in an empty area of the schematic, while holding down an other predefined keyboard key and rolling the mouse scrolling device in an upward direction.

Abstract: A system to improve a voltage-controlled oscillator may include a voltage-controlled oscillator. The system may also include a switch to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain.

Abstract: A multiple output voltage regulator includes a voltage regulator amplifier, a first device, and a second device. The voltage regulator amplifier includes a first input configured to receive a reference voltage and an output. The first device includes a first terminal, a second terminal, and a control terminal. The control terminal of the first device is coupled to the output of the voltage regulator amplifier, the first terminal of the first device is coupled to a power supply terminal, and the second terminal of the first device is coupled to a second input of the voltage regulator amplifier (to provide negative feedback) and is configured to be coupled to one side of a first load. The second device includes a first terminal, a second terminal, and a control terminal.

Abstract: A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes.

Abstract: An oscillating circuit includes a charge pump, a loop filter and a voltage controlled oscillator. The charge pump and the loop filter generates a differential voltage signal. The loop filter is responsive to the differential voltage signal and generates a filtered differential voltage control signal that is proportional to the differential voltage signal. The voltage controlled oscillator is responsive to the filtered differential voltage control signal and generates a periodic signal that has a frequency that corresponds to the filtered differential voltage control signal.

Abstract: A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical hierarchical design applications, by assigning, from a schematic of the integrated circuit, a viewable scope of a block element desired for traversing. Opening the viewable scope of the block element, by using a mouse scrolling device to cause a cursor to highlight and roll in a downward direction over the highlighted block element, while holding down a predefined keyboard key. Then closing the viewable scope of the block element, by causing the cursor to be positioned in an empty area of the schematic, while holding down an other predefined keyboard key and rolling the mouse scrolling device in an upward direction.

Abstract: An apparatus for biasing a body voltage of a silicon-on-insulator transistor includes an operational amplifier that generates an output voltage that is proportional to the voltage difference between a desired gate-source threshold voltage and a reference voltage. A reference biasing transistor has a gate that is electrically coupled to the output. A reference mirror transistor has both a gate and a drain that are electrically coupled to the current source node, and also has a body that is electrically coupled to the drain of the reference biasing transistor. A device biasing transistor has a gate that is electrically coupled to the output voltage and has a drain that is electrically coupled to the body of the silicon-on-insulator transistor. The device biasing transistor maintains a voltage at the body of the silicon-on-insulator transistor so that it has a gate-source threshold voltage within a predetermined range of the desired gate-source threshold voltage.

Abstract: An apparatus for biasing a body voltage of a silicon-on-insulator transistor includes an operational amplifier that generates an output voltage that is proportional to the voltage difference between a desired gate-source threshold voltage and a reference voltage. A reference biasing transistor has a gate that is electrically coupled to the output. A reference mirror transistor has both a gate and a drain that are electrically coupled to the current source node, and also has a body that is electrically coupled to the drain of the reference biasing transistor. A device biasing transistor has a gate that is electrically coupled to the output voltage and has a drain that is electrically coupled to the body of the silicon-on-insulator transistor. The device biasing transistor maintains a voltage at the body of the silicon-on-insulator transistor so that it has a gate-source threshold voltage within a predetermined range of the desired gate-source threshold voltage.

Abstract: A digital system generates a single-phase master clock and distributes it to multiple cards and chips incorporating the functional logic of the system. A circuit in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.