Patents by Inventor James J. Roman
James J. Roman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9111902Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: GrantFiled: January 21, 2014Date of Patent: August 18, 2015Assignee: Invensas CorporationInventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Publication number: 20140131836Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: Invensas CorporationInventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Patent number: 8633589Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: GrantFiled: October 2, 2007Date of Patent: January 21, 2014Assignee: Invensas CorporationInventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Patent number: 7964508Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: GrantFiled: August 21, 2008Date of Patent: June 21, 2011Assignee: Allvia, Inc.Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Patent number: 7510928Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: GrantFiled: May 5, 2006Date of Patent: March 31, 2009Assignee: Tru-Si Technologies, Inc.Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Publication number: 20080311749Abstract: A portion of a conductive layer (310, 910) provides a capacitor electrode (310.0, 910.0). Dielectric trenches (410, 414, 510) are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric (320) can be formed by anodizing tantalum while a nickel layer (314) protects an underlying copper (310) from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer (610) is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.Type: ApplicationFiled: August 21, 2008Publication date: December 18, 2008Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Publication number: 20080164574Abstract: A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive material (520, 540, 1110, 1130) is formed in the opening and in contact with the top side pad. The conductive material also provides a backside contact pad (1310). Other embodiments are also provided.Type: ApplicationFiled: March 19, 2008Publication date: July 10, 2008Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Publication number: 20080136038Abstract: A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (150C), by forming an opening (220) through a top side contact pad (150C) and the semiconductor substrate (110). Conductive material (520, 540, 1110, 1130) is formed in the opening and in contact with the top side pad. The conductive material also provides a backside contact pad (1310). Other embodiments are also provided.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Sergey Savastiouk, Valentin Kosenko, James J. Roman
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Patent number: 6845184Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.Type: GrantFiled: April 20, 1999Date of Patent: January 18, 2005Assignee: Fujitsu LimitedInventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
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Patent number: 6690845Abstract: Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.Type: GrantFiled: May 19, 2000Date of Patent: February 10, 2004Assignee: Fujitsu LimitedInventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
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Patent number: 6611635Abstract: Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.Type: GrantFiled: April 20, 1999Date of Patent: August 26, 2003Assignee: Fujitsu LimitedInventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
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Patent number: 6391220Abstract: Methods and articles used to fabricate flexible circuit structures are disclosed. The methods include depositing a release layer on substrate, and then forming a conductive laminate on the release layer. After the release layer is formed, the conductive laminate can be easily separated by the substrate to eventually form a flexible circuit structure.Type: GrantFiled: August 18, 1999Date of Patent: May 21, 2002Assignee: Fujitsu Limited, Inc.Inventors: Lei Zhang, Solomon Beilin, Som S. Swamy, James J. Roman
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Patent number: 6343171Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.Type: GrantFiled: April 20, 1999Date of Patent: January 29, 2002Assignee: Fujitsu LimitedInventors: Tetsuzo Yoshimura, Yashuhito Takahashi, Masaaki Inao, Michael G. Lee, William Chou, Solomon I. Beilin, Wen-chou Vincent Wang, James J. Roman, Thomas J. Massingill
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Patent number: 6226171Abstract: Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.Type: GrantFiled: January 8, 1999Date of Patent: May 1, 2001Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, Michael G. Lee, David Dung Ngo, Michael G. Peters, James J. Roman, Yasuhito Takahashi
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Patent number: 6102710Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: April 30, 1998Date of Patent: August 15, 2000Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 6090214Abstract: A chemical mechanical cleaning method utilizes an ammonium persulphate solution with simultaneous mechanical brushing to remove residual slurry particles from copper surfaces. The pH of the solution is selected to electrostatically repel charged slurry particles from the copper surface.Type: GrantFiled: June 22, 1998Date of Patent: July 18, 2000Assignee: Fujitsu LimitedInventors: Dashun Steve Zhou, Solomon I. Beilin, James J. Roman
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Patent number: 5854534Abstract: An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected.Type: GrantFiled: November 16, 1995Date of Patent: December 29, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou Vincent Wang, Larry L. Moresco, Teruo Murase
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Patent number: 5778529Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: May 22, 1996Date of Patent: July 14, 1998Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-Chou Vincent Wang
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Patent number: 5580831Abstract: The present invention is a method for producing alignment marks on opposite faces of a generally flat substrate such as a semiconductor wafer. First, reference cuts are produced at the edges of the substrate at four points around the wafer. Next, the center line is determined on the first face of the substrate between two oppositely disposed reference cuts. First and second grooves are then cut in the first face of the substrate a first predetermined distance from the first center line. Third and fourth grooves are cut in the first face perpendicular to and through the first and second grooves at the first predetermined distance from the second reference cut forming crosshair alignment patterns. Next, the center line is determined on the second face of the substrate between the third and fourth reference cuts, and fifth and sixth grooves are cut in the second face of the substrate a second predetermined distance from the second center line.Type: GrantFiled: July 28, 1993Date of Patent: December 3, 1996Assignee: Fujitsu LimitedInventor: James J. Roman
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Patent number: 5544017Abstract: A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.Type: GrantFiled: July 19, 1994Date of Patent: August 6, 1996Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Teruo Murase, Michael G. Peters, James J. Roman, Som S. Swamy, Wen-chou V. Wang