Patents by Inventor James J. Roman

James J. Roman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5458731
    Abstract: Methods for examining a structure etched in a material layer are disclosed. An inspection aperture next to the structure is formed without appreciably disturbing the etching of the structure. The inspection aperture is formed such that it merges with a portion of the structure's perimeter wall to create an inspection window through which the structure may be readily observed. The observed image of the perimeter wall and bottom of the structure is comparable to that obtained by cleaving, and is achieved without destroying the wafer or substrate on which the etched structure is formed. An etch mark designed to implement the method is also disclosed.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: October 17, 1995
    Assignee: Fujitsu Limited
    Inventors: James J. Roman, William T. Chou
  • Patent number: 5419038
    Abstract: A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: May 30, 1995
    Assignee: Fujitsu Limited
    Inventors: Wen-chou V. Wang, Solomon I. Beilin, William T. Chou, David Kudzuma, Michael G. Lee, Michael G. Peters, James J. Roman, Som S. Swamy