Abstract: Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.

Abstract: Embodiments include methods, systems and computer readable media configured to execute a first kernel (e.g. compute or graphics kernel) with reduced intermediate state storage resource requirements. These include executing a first and second (e.g. prefetch) kernel on a data-parallel processor, such that the second kernel begins executing before the first kernel. The second kernel performs memory operations that are based upon at least a subset of memory operations in the first kernel.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: Methods of operating a serial data bus are disclosed that generate two-level bridge symbols to insert between four-level symbols on a data lane, to reduce voltage deltas on the data lane during data transmission. These methods may be utilized on multiple data lanes of the serial data bus.

Abstract: Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.

Abstract: Methods, systems and computer readable storage mediums for more efficient and flexible scheduling of tasks on an asymmetric processing system having at least one host processor and one or more slave processors, are disclosed. An example embodiment includes, determining a data access requirement of a task, comparing the data access requirement to respective local memories of the one or more slave processors selecting a slave processor from the one or more slave processors based upon the comparing, and running the task on the selected slave processor.

Abstract: Methods, systems and computer readable storage mediums for more efficient and flexible scheduling of tasks on an asymmetric processing system having at least one host processor and one or more slave processors, are disclosed. An example embodiment includes, determining a data access requirement of a task, comparing the data access requirement to respective local memories of the one or more slave processors selecting a slave processor from the one or more slave processors based upon the comparing, and running the task on the selected slave processor.

Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Abstract: Embodiments include methods, systems and computer readable media configured to execute a first kernel (e.g. compute or graphics kernel) with reduced intermediate state storage resource requirements. These include executing a first and second (e.g. prefetch) kernel on a data-parallel processor, such that the second kernel begins executing before the first kernel. The second kernel performs memory operations that are based upon at least a subset of memory operations in the first kernel.

Abstract: Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests.

Abstract: A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.

Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Abstract: A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each region of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.

Abstract: A compression technique includes storing respective fixed-size symbols for each of a plurality of words in a data block, e.g., a cache line, into a symbol portion of a compressed data block, e.g., a compressed cache line, where each of the symbols provides information about a corresponding one of the words in the data block. Up to a first plurality of data segments are stored in a data portion of the compressed data block, each data segment corresponds to a unique one of the symbols in the compressed data block and a unique one of the words in the cache line. Up to a second plurality of dictionary entries are stored in the data portion of the compressed cache line. The dictionary entries can correspond to multiple ones of the symbols.

Abstract: Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests.