Abstract: The present invention provides a memory system that caches method frames using multiple stack cache management units to provide access to multiple portions of the method frames. In some embodiments of the invention, a memory system includes a main memory circuit, a first stack cache management unit, and a second stack cache management unit. The first stack cache management unit is configured to cache a first frame component of a first method frame and a second frame component of a second method frame. The second stack cache management unit is configured to cache a second frame component of the first method frame and a first frame component of the second method frame. Some embodiments of the memory system also includes a main memory cache coupled between the main memory circuit and the stack cache management units. The first frame components of the method frames can be, for example, the operand stacks method frames.

Abstract: An instruction accelerator which includes a processor and an associative memory. The processor is coupled to receive a stream of instructions and a corresponding stream of instruction identifier values. The instructions include at least one non-quick instruction which has a first associated data set which must be accessed prior to executing the non-quick instruction. A memory, which is coupled to the processor, stores one or more instruction identifier values and one or more associated data sets. The memory receives the stream of instruction identifier values. When a current instruction identifier value in the stream of instruction identifier values matches an instruction identifier value stored in the memory, an associated data set is accessed from the memory.

Abstract: The present invention provides methods for storing method frames in a multi-stack memory architecture to provide access to multiple portions of the method frame. In one embodiment, a first frame component of a first method frame is stored in a first stack. A second component of the first method frame is stored in a second stack. A first component of a second method frame is stored in the second stack and a second frame component of the second method frame is stored in the first stack. In some embodiments, the first frame components of the first and second stacks are operand stacks, while the second frame components are arguments and local variable areas.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data transfers between the stack-based computing system and the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. Specifically, when the stack-based computing system is pushing data onto the stack and a spill condition occurs, the spill control unit transfers data from the bottom of the stack cache to the stack so that the top portion of the stack remains in the stack cache.

Abstract: An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction sequences and supplies an execution unit with a single equivalent folded operation thereby reducing processing cycles otherwise required for execution of multiple operations corresponding to the multiple instructions of the folded instruction sequence. Instruction decoder embodiments described herein provide for folding of two, three, four, or more instruction folding. For example, in one instruction decoder embodiment described herein, two load instructions and a store instruction can be folded into execution of operation corresponding to an instruction appearing therebetween in the instruction sequence.

Abstract: A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

Abstract: An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element.

Abstract: A method and apparatus for accelerating the execution of an object oriented computer program having a plurality of objects. In one embodiment, each of the objects includes an object header and object data which are stored in a memory. Moreover, each of the objects is associated with a corresponding set of methods (or functions). A typical object oriented program only maintains one copy of a method which is accessed by more than one object. However, in the present invention, each method is copied and stored in a memory, such that each object has a dedicated set of methods stored in memory. For example, if a first object and a second object require access to the same method, then a first copy of this method is provided for the first object, and a second copy of this method is provided for the second object. Providing each object with a dedicated set of methods minimizes the levels of indirection required to access the methods, and thereby accelerates the execution of instructions which access the objects.

Abstract: A computer processor includes a number of register pairs LOCKADDR/LOCKCOUNT. In each pair, the LOCKADDR/LOCKCOUNT register is to hold a value that identifies a lock for a computer resource. When a lock instruction issues, the corresponding LOCKCOUNT register is incremented. When an unlock instruction issues, the corresponding LOCKCOUNT register is decremented. The lock is freed when a count associated with the LOCKCOUNT register is decremented to zero. This scheme provides fast locking and unlocking in many frequently occurring situations. In some embodiments, the LOCKCOUNT registers are omitted, and the lock is freed on any unlock instruction corresponding to the lock. In some embodiments, a computer object includes a header which includes a pointer to a class structure. The class structure is aligned on a 4-byte boundary, and therefore two LSBs of the pointer to the class structure are zero and are not stored in the header.

Abstract: A pointer-specific instruction variant replacement mechanism facilitates an exact write barrier, i.e., a write barrier specific to pointer stores and transparent to non-pointer stores. Pointer store specific instruction replacement allows some implementations to provide an exact barrier specific to the particular set of intergenerational pointer stores that are of interest to a particular garbage collection method or combination of methods. The exact identification of pointer stores herein does not require tags encoded in-line with collected memory storage and does not require non-standard word sizes to support such tags. In one embodiment, a non-quick to quick translator cache provides pointer specific store instruction replacement. In another, self modifying code provides pointer specific store instruction replacement.

Abstract: A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

Abstract: A partially relocated object identifier store including "copy from" identifier and "copy to" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object without software trap handler overhead. Optional "How far" indication storage facilitates differentiation by the write barrier logic between a copied portion and an uncopied portion of the partially relocated memory object. An optional "mode" indication facilitates differentiation by the write barrier logic between a copy phase and a pointer update phase of relocation by the garbage collector implementation. In some embodiments, pointer update and copying phases may overlap. "Copy to" identifier storage facilitates broadcast of a store-oriented memory access to the FromSpace instance to both FromSpace and ToSpace instances.

Abstract: A write barrier to stores into a partially relocated large or popular memory object facilitates bounded pause time implementations of relocating garbage collectors, including e.g., copying collectors, generational collectors, and collectors providing compaction. Such a write barrier allows a garbage collector implementation to interrupt relocation of large or popular memory objects so as to meet bounded pause time guarantees. A partially relocated object identifier store including "copy from" identifier storage accessible to write barrier logic allows the write barrier logic to maintain consistency between FromSpace and ToSpace instances of a partially relocated memory object. "Copy from" identifier storage allows the write barrier logic, or a trap handler responsive thereto, to broadcast a store-oriented memory access targeting the FromSpace instance to both FromSpace and ToSpace instances.

Abstract: A partially relocated object identifier store including "copy from" and "copy to" identifier storage accessible to write and read barrier logic allows the write and read barrier logic to selectively direct store- and load-oriented accesses to an appropriate FromSpace or ToSpace instance of a partially relocated memory object, in accordance with the memory object's partial relocation state. In some embodiments, the barriers trap to a partially relocated object trap handler. In other embodiments, the write barrier itself directs accesses without software trap handler overheads. Optional "how far" indication storage facilitates differentiation by the barrier logic, or by the partially relocated object trap handler, between a copied portion and an uncopied portion of the partially relocated memory object.

Abstract: Architectural support is provided for trapping of garbage collection page boundary crossing pointer stores. Identification of pointer stores as boundary crossing is performed by a store barrier responsive to a garbage collection page mask that is programmably encoded to define a garbage collection page size. The write barrier and garbage collection page mask provide a programmably-flexible definition of garbage collection page size and therefore of boundary crossing pointer stores to be trapped, affording a garbage collector implementer with support for a wide variety of generational garbage collection methods, including train algorithm type methods to managing mature portions of a generationally collected memory space. Pointer specific store instruction replacement allows implementations that provide an exact barrier not only to pointer stores, but more particularly to pointer stores crossing programmably defined garbage collection page boundaries.