Abstract: System and methods for displaying one or more assets on a client device based on device characteristics are provided. Code is transmitted to a client device. The code, when executed by the client device, causes a processor of the client device to determine a first device characteristic of the client device. A first layout may be selected based on the first device characteristic. The layout may include one or more cards. Each card may correspond to one or more assets. Each card may be modified based on a corresponding card characteristic. One or more assets may be requested. The assets may be displayed on the first client device. The code may be transmitted to another client device, which may select a different layout based on a different device characteristic.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: A radio frequency (RF) communications system may include an RF transmitter having multicarrier transmitter circuitry that transmits frequency bands over a frequency range. A controller may selectively transmit real information over at least one of the frequency bands and selectively transmits fake information within the frequency range. The controller's operation is based on embedded machine learning model and real-time effectiveness feedback from built-in spectral analyzer. An RF receiver receives the real information from the RF transmitter.

Abstract: A system includes a measurement device having an electronic distance measurement (EDM) instrument, and at least one processor coupled to the EDM instrument. The at least one processor is configured to localize the measurement device relative to a design model, the measurement device being physically located at a measurement location, automatically generate, for at least one design element in the design model, a plurality of sample directions, control the EDM instrument to automatically perform measurements in the plurality of sample directions, and generate and output a verification result indicating a relation between the at least one design element and at least one object corresponding to the at least one design element, based on a shape of the at least one design element and measurement data of the measurements.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Abstract: Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: A communications system may include a transmitter having spreading stages configured to spread a common modulated baseband input data stream based upon respective coefficient sequences; a plurality of upconverters, each having a different frequency; and an RF output stage that generates an RF output signal. A receiver may include an RF input stage that receives an RF input signal, a plurality of downconverters, a plurality of despreading stages, and a demodulator coupled to the despreading stages.

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: A communications system may include a transmitter having spreading stages configured to spread a common modulated baseband input data stream based upon respective coefficient sequences; a plurality of upconverters, each having a different frequency; and an RF output stage that generates an RF output signal. A receiver may include an RF input stage that receives an RF input signal, a plurality of downconverters, a plurality of despreading stages, and a demodulator coupled to the despreading stages.

Abstract: A radio frequency (RF) communications system may include an RF transmitter having multicarrier transmitter circuitry that transmits frequency bands over a frequency range. A controller may selectively transmit real information over at least one of the frequency bands and selectively transmits fake information within the frequency range. The controller's operation is based on embedded machine learning model and real-time effectiveness feedback from built-in spectral analyzer. An RF receiver receives the real information from the RF transmitter.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: A flexible swivel has a flexible toroid described by an internal major diameter, a fore ring, a body, and an aft ring. The flexible toroid is attached to the fore ring. The fore ring is attached with a rotatable fore joint to the front of the body. The aft ring is attached to the back of the body.

Abstract: A blank for forming a display ready case includes a front panel, a top panel, a rear panel, a bottom panel, and a bottom end panel arranged in a longitudinal direction and coupled together by a plurality of fold lines extending in a transverse direction. A first front side panel and a second front side panel extend from opposing sides of the front panel in the transverse direction. A front end panel extends from the front panel in the longitudinal direction, and a first front end side panel and a second front end side panel extend from opposing sides of the front end panel in the transverse direction. An access region separates the front panel from the front end panel. A line of weakness separates the first front side panel and the second front side panel from the first front end side panel and the second front end side panel.

Abstract: A flexible swivel has a flexible toroid described by an internal major diameter, a fore ring, a body, and an aft ring. The flexible toroid is attached to the fore ring. The fore ring is attached with a rotatable fore joint to the front of the body. The aft ring is attached to the back of the body.

Abstract: A nasal delivery device can include a nasal prong and an activation member. The nasal prong can have an opening at a top and bottom portion of the prong to allow for the passage of an aerosolized treatment agent through the nasal prong. The activation member can be positioned on the nasal delivery device at a location that is spaced apart from the subject's oral cavity when the nasal prong is received into the nostril of the subject. The activation member can detect a desired exhalation state of the subject and upon detection of the desired exhalation state, the activation member activates the delivery of the aerosolized treatment agent.