Abstract: A nasal delivery device can include a nasal prong and an activation member. The nasal prong can have an opening at a top and bottom portion of the prong to allow for the passage of an aerosolized treatment agent through the nasal prong. The activation member can be positioned on the nasal delivery device at a location that is spaced apart from the subject's oral cavity when the nasal prong is received into the nostril of the subject. The activation member can detect a desired exhalation state of the subject and upon detection of the desired exhalation state, the activation member activates the delivery of the aerosolized treatment agent.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: A flexible swivel has a flexible toroid described by an internal major diameter, a fore ring, a body, and an aft ring. The flexible toroid is attached to the fore ring. The fore ring is attached with a rotatable fore joint to the front of the body. The aft ring is attached to the back of the body.

Abstract: A flexible swivel has a flexible toroid described by an internal major diameter, a fore ring, a body, and an aft ring. The flexible toroid is attached to the fore ring. The fore ring is attached with a rotatable fore joint to the front of the body. The aft ring is attached to the back of the body.

Abstract: Systems (400) and methods for reducing a number of cyclostationary features in a transmitted signal. The methods comprise: obtaining by a transmitter a discrete-time IF signal comprising a sequence of samples all having a same sample duration; performing operations by a sub-sample dithering processing device of the transmitter to modify a sample timing of the discrete-time IF signal by decreasing or increasing a duration of at least one first sample of the sequence using a digital signal processing technique in a digital domain; converting the discrete-time IF signal to an RF signal; and transmitting the RF signal having a reduced number of cyclo stationary features.

Abstract: A video game includes a plurality of components providing for opportunities for increased social interaction of users playing the video game. The video game may be a music-based video game, and a server may provide content of the video game to game devices for play at predefined times.

Abstract: Systems (400) and methods for removing dither introduced into a transmitted RF signal. The method comprising: receiving, by a receiver, the transmitted RF signal; converting, by the receiver, the transmitted RF signal into a discrete-time IF signal comprising a sequence of samples, where at least a first sample of said samples has a first sample duration different than a second sample duration of at least a second sample of said samples; and performing operations by a sub-sample dither removal device of the receiver to modify a sample timing of the discrete-time IF signal by decreasing or increasing the first sample duration of the first sample using a digital signal processing technique in a digital domain.

Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

Abstract: Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.

Abstract: A case packing system for loading articles into containers includes an article conveyor for conveying articles, a case conveyor for conveying containers, and first, second, and third bins. A first robotic mechanism moves articles on the article conveyor to the first, second, and third bins. A second robotic mechanism moves articles from the first, second, and third bins to containers on the case conveyor. A controller operatively coupled to the first robotic mechanism and the second robotic mechanism is configured to pick and place with the first robotic mechanism one or more conveyed articles into the first, second, and third bins, and grab and load with the second robotic mechanism one or more articles from the first, second, and third bins into containers on the case conveyor.

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

Abstract: This application is directed to an indexing system for graph data. In particular implementations, the indexing system uses a database index infrastructure that provides for flexible search capability to data objects and associations between data objects. Particular embodiments relate to an indexing system for storing and serving information modeled as a graph that includes nodes and edges that define associations or relationships between nodes that the edges connect in the graph.

Abstract: A video game includes user generated content. The video game may be a music-based video game. Users may determine content to be played, and a server may provide the content to game devices for play, for example at predefined times, and/or to predetermined game players.

Abstract: A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

Abstract: Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.

Abstract: An electronic device may include a speaker, and audio circuitry coupled to the speaker. The audio circuitry may generate digitized samples of an audio waveform signal, and compare each digitized sample of the audio waveform signal to a threshold. The audio circuitry may when a given digitized sample is above the threshold, then apply a compression operation to the given digitized sample and successive digitized samples for a set time period, and when the given digitized sample is below the threshold and not within the set time period, then not apply the compression operation.

Abstract: Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

Abstract: This application is directed to an indexing system for graph data. In particular implementations, the indexing system uses a database index infrastructure that provides for flexible search capability to data objects and associations between data objects. Particular embodiments relate to an indexing system for storing and serving information modeled as a graph that includes nodes and edges that define associations or relationships between nodes that the edges connect in the graph.

Abstract: Systems (100) and methods (400) for transducer volume bias control. The methods involve: obtaining an audio signal that is to be output from first and second transducers (102, 202) of an electronic device (100); and dynamically changing spectral content of the audio signal to at least one of the first and second transducers as a transducer volume level increases and decreases. The first transducer is disposed on a first side (108) of the electronic device. The second transducer is disposed on a second side (204) that is different than the first side of the electronic device. The first and second transducers have imbalanced capabilities.