Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A method of modifying polarity of light is provided. The light propagates through a first transverse plane and has known polarization states in respective cells of the first transverse plane. A first retardation compensator having respective waveplates matching the cells then changes the polarity of the light so that light propagating through a second transverse plane is circularly polarized across the entire second transverse plane. A second retardation compensator includes a plurality of quarter waveplates that change the polarization of the circularly polarized light, so that light passing through a third transverse plane is linearly polarized. The crystal alignment of the quarter waveplates and their shape and configuration are selected so that the direction of the polarization is normal to a radius from a single point.

Abstract: Some embodiments describe techniques that relate to hybrid graphics display power management. In one embodiment, data corresponding to one or more image frames of a video stream are stored in a local frame buffer. A display device (e.g., an LCD) may then be driven based on the stored data in the local frame buffer or a video stream from a graphics controller. Other embodiments are also described.

Abstract: Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.

Abstract: Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.

Abstract: Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.

Abstract: A computer includes a wireless personal area network (WPAN) interface, a wireless local area network (WLAN) interface and a wireless wide area network (WWAN) interface. A device communicating with the wireless personal area network can command the computer to perform actions using the wireless local area network interface or wireless wide area network interface.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.

Abstract: Systems and methods of power management provide for controlling the idleness of a processor based on an operating system schedule. The idleness of at least one device is synchronized with the idleness of the processor. Idleness synchronization may involve deferring bus transactions, suspending memory refresh, turning off power to clock sources and turning off power to combinatorial logic during an idle window in the OS schedule.

Abstract: A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.

Abstract: A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

Abstract: A reconfigurable zone plate lens is disclosed. Some embodiments may include a central annular element having a first a first circumference centered about a central axis. Embodiments may also include a plurality of concentric annular elements of increasing circumference centered about the central axis and the central annular element, where each annular element is positioned around an annular element having a smaller circumference. The annular elements of some embodiments may each be adapted to be in either an active or inactive state where the active and inactive annular elements form a plurality of alternating active rings and inactive rings. Each active ring may include one or more annular elements in an active state and each inactive ring may include one or more annular elements in an inactive state. Each annular element may include one or more liquid crystal display (LCD) elements or micromirrors. Other embodiments are disclosed and claimed.

Abstract: A method is described that involves operating a computing system within a normal on state and transitioning from the normal on state to a main CPU/OS based state. In the main CPU/OS based state one or more components of the computing system are inactivated so as to cause the computing system to consume less power in the main CPU/OS based state than in the normal on state. The computing system is able to execute software application routines on a main CPU and a main OS of the computing system while in the main CPU/OS based state.

Abstract: Techniques and structures are disclosed for providing service related information to wireless users within a wireless network.

Abstract: A processor may perform real-time event processing of real-time events in a manner that enables a radio module equipped computer system to operate in accordance with a wireless communication protocol using host processor baseband processing. In accordance with one embodiment, the processor may perform real-time event processing by halting a process in response to receiving a real-time event, handling the event, then returning to the process. In accordance with another embodiment, the processor may perform real-time event processing on a non-symetric processing core integrated with a primary host processor core that shares the same L2 cache.

Abstract: Methods and apparatus are disclosed for communicating via a radio channel to reduce radio frequency (RF) interference between transceiver systems within an electronic device.