Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values.

Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: Graphics data representing color values of pixels are compressed into a data structure. Each pixel has a color value that results from the combination of a luma component and chroma components. The number of bits representing the luma and chroma components of a pixel are reduced to less than eight bits, and the luma components of at least four pixels and at least two chroma components are combined into a data structure r bits in length. The number of bits of the data structure is derived from r=2s, where s is an integer greater than or equal to five.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: A system and method for storing data in memory in either a packed or unpacked format contiguously and providing retrieved data in an unpacked format. The memory system includes a memory having packed and unpacked data stored in lines of data and a register to store a line of data it receives from the memory. Further included in the system is a selection circuit coupled to receive data from both the memory and the register. The selection circuit selects a portion of data from the lines of data presented to it by the memory and the register to be provided to a data bus according to a select signal provided by a memory address generator. The select signal is calculated by the memory address generator from an expected address at which the data is expected to be located. A second register and a second selection circuit may also be included in the memory system.

Abstract: A direct memory access (DMA) controller for controlling memory access operations in a memory. During a memory access operation, the DMA controller executes a chain of DMA commands stored in a memory and having a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, regardless of whether the last DMA command of the command chain has been executed by the DMA controller. The self-linking mode is entered when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be a link address which points to the last executed DMA command, or alternatively, a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.

Abstract: The invention relates to a hot melt processable pressure sensitive adhesive comprising at least one elastomer, organophilic clay plate-like particles, and at least one non-volatile organophilic exfoliating agent. Also disclosed are articles prepared therefrom and methods pertaining thereto.

Abstract: A method and apparatus for mapping graphics data of a texture map into virtual two-dimensional (2D) memory arrays implemented in a one-dimensional memory space. The texture map is partitioned into 2u+v two-dimensional arrays having dimensions of 2m bytes×2n rows. The graphics data is then mapped from a respective two-dimensional array into the one-dimensional memory space by calculating an offset value based on the coordinates of a respective texel of the texture map and subsequently reordering the offset value to produce a memory address value. The order of the offset value is, from least to most significant bits, a first group of m bits, a second group of u bits, a third group of n bits, and a fourth group of v bits. The order of the offset value is reordered to, from least to most significant bits, first, third, second, and fourth groups. The resulting value produces a memory address for the one-dimensional memory space.

Abstract: The present invention is directed to a primer composition. The primer composition comprises a maleated thermoplastic elastomer, a non-halogenated polyolefin, and a resin. In some embodiments, the primer comprises a crosslinking agent, for example 2,4-bis(trichloromethyl)-6-4′-methoxyphenyl-sym-triazine. In other embodiments, the primer comprises an epoxy.

Abstract: A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective weight value. A first intermediate value is interpolated for a first offset value from a first plurality of the input sample values and a second intermediate value is interpolated for a second offset value from a second plurality of the input sample values. The offset values are representative of the weight values of the input samples of the respective plurality of the input samples. The first and second intermediate values are combined to produce a resultant value which is subsequently blended with the remaining input sample values of the plurality in accordance with respective scaling values assigned to the resultant value and the remaining input sample values.

Abstract: The invention relates to a hot melt processable pressure sensitive adhesive comprising at least one elastomer, organophilic clay plate-like particles, and at least one non-volatile organophilic exfoliating agent. Also disclosed are articles prepared therefrom and methods pertaining thereto.

Abstract: A head testing apparatus is provided for testing a data recording head. The apparatus includes a test volume, a magnetic field source, a holder and a thermoelectric source. The test volume is adapted to receive the head, and the magnetic field source is positioned to generate a magnetic field within the test volume. The holder is adapted to hold the head and position the head within the test volume. The thermoelectric source is positioned to contact the head when the head is positioned within the test volume by the holder.

Abstract: An apparatus and method for controlling a motor/blower system to provide a constant fluid flow by iteratively loading revised stator frequency values and stator voltage values to a variable frequency drive. Target DC bus current values corresponding to constant fluid flow rates are predetermined and stored as a function of the desired fluid flow rate, the operating frequency, and system specific constants or calculated by the controller as a function thereof during system operation. Actual DC bus current is measured with a current sensor and compared with the target DC bus current. Operating frequency is estimated using a PI controller based on the difference between measured and target DC bus current values. Operating voltage values corresponding to operating frequencies and system specific constants are predetermined and stored in memory or calculated by the controller during system operation. An updated target DC bus current, operating frequency and operating voltage are determined upon each iteration.

Abstract: A method and system for performing multi-sample rendering of antialiased images. The pixels of an image are sampled in accordance with sampling patterns. Each of the sampling patterns defines sampling locations at which sample values are calculated. A value for a pixel in the image is calculated by combining respective sample values.

Abstract: A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated reciprocal term from the first memory and a selected reciprocal error term from the second memory to provide the reciprocal. The selected estimated reciprocal term and the selected reciprocal error term correspond to at least a portion of a divisor. The apparatus includes a multiplier for multiplying a dividend by the reciprocal to generate a quotient. The method includes the step of looking up an estimated reciprocal term in a first lookup table stored in a first computer memory wherein the estimated reciprocal term corresponds to at least a portion of a given divisor. A reciprocal error term is looked up in a second lookup table stored in a second computer memory, the error term corresponds to at least a portion of the divisor.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.

Abstract: An apparatus and method for controlling a motor/blower system to provide a constant fluid flow by iteratively loading revised stator frequency values and stator voltage values to a variable frequency drive. Target DC bus current values corresponding to constant fluid flow rates are predetermined and stored as a function of the desired fluid flow rate, the operating frequency, and system specific constants or calculated by the controller as a function thereof during system operation. Actual DC bus current is measured with a current sensor and compared with the target DC bus current. Operating frequency is estimated using a PI controller based on the difference between measured and target DC bus current values. Operating voltage values corresponding to operating frequencies and system specific constants are predetermined and stored in memory or calculated by the controller during system operation. An updated target DC bus current, operating frequency and operating voltage are determined upon each iteration.