Abstract: Embodiments described herein can include multi-layer circuits within a liquid crystal polymer (LCP) material to define a 3-D interconnect structure that connects the microelectronics features, devices, components and electrical interfaces. In addition, mechanical functions can be embedded in a fashion and proximity such that the embedded electronics can interface and interact with each other as well as introduced conditions relevant to the function of the device and the outside world or environment it is exposed to.

Abstract: A facepiece having one or more airflow baffles that have an antipathogen surface is disclosed. The facepiece has a main body with a geometry configured to fit on a human face and cover the human's mouth and nose. The main body defines an interior cavity between the main body and the human's face. One or more straps extend from the main body and are configured to extend around the ears or head of a human such that the main body is held on the human's face. The facepiece includes one or more baffles disposed on the main body and in an airflow path between the interior cavity and an external environment. The one or more baffles have a first surface disposed to deflect air traveling along the airflow path. The first surface has a metal layer exposed to air traveling along the airflow path.

Abstract: A circuit board having a plurality of conductive layers including a first conductive layer and a second conductive layer is provided. The circuit board includes a plurality of non-conductive layers in-between respective conductive layers of the plurality of conductive layers. The plurality of non-conductive layers include at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. At least one collapsed stud bump extends at least partially through the first non-conductive layer to electrically couple the first conductive layer to the second conductive layer.

Abstract: Embodiments described herein can include multi-layer circuits within a liquid crystal polymer (LCP) material to define a 3-D interconnect structure that connects the microelectronics features, devices, components and electrical interfaces. In addition, mechanical functions can be embedded in a fashion and proximity such that the embedded electronics can interface and interact with each other as well as introduced conditions relevant to the function of the device and the outside world or environment it is exposed to.

Abstract: A facepiece comprising a main body having a geometry configured to fit on a human face and cover the human's mouth and nose is provided. The main body defines an interior cavity between the main body and the human's face. The facepiece also includes one or more straps extending from the main body and configured to extend around the ears or head of a human such that the main body is held on the human's face. The main body includes a filter defining a plurality of airflow torture paths extending therethrough between the interior cavity and an external environment. The filter includes three or more layers of airflow path defining features, each airflow path defining feature providing a passageway for air to pass therethrough. The path defining features in adjacent layers are fluidly coupled but offset to form the airflow torture paths.

Abstract: A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures.

Abstract: A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

Abstract: A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.

Abstract: An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

Abstract: An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

Abstract: A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract: A surface mount electrical interconnect is disclosed that provides an interface between a PCB and solder balls of a BGA device. The electrical interconnect includes a socket substrate and a plurality of electrically conductive contact members. The socket substrate has a first layer with a plurality of openings configured to receive solder balls of the BGA device and has a second layer with a plurality of slots defined therethrough that correspond to the plurality of openings. The contact members may be disposed in the openings in the first layer and through the plurality of slots of the second layer of the socket substrate. The contact members can be configured to engage a top portion, a center diameter, and a lower portion of the solder ball of the BGA device. Each contact member electrically couples a solder ball on the BGA device to the PCB.

Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

Abstract: An array of composite polymer-metal contact members adapted to form solder free electrical connections with a first circuit member. The contact members include a resilient polymeric base layer and an array of metalized traces printed on selected portions of the base layer. Conductive plating is applied to the metalized layer to create an array of conductive paths. The resilient polymeric base layer, the metalized layer, and the conductive plating have an aggregate spring constant sufficient to maintain distal portions of the contact members in a cantilevered configuration and to form a stable electrical connection between the distal portions and the first circuit member solely by compressive engagement.

Abstract: A surface mount electrical interconnect adapted to provide an interface between contact pads on an LGA device and a PCB. The electrical interconnect includes a socket substrate having a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of contact members are located in the socket substrate such that first contact tips are located proximate the first openings, second contact tips are located proximate the second openings, and center portions located in the center openings.

Abstract: A surface mount electrical interconnect to provide an interface between a PCB and contacts on an integrated circuit device. The electrical interconnect includes a substrate with a plurality of recesses arranged along a first surface to correspond to the contacts on the integrated circuit device. Contact members are located in a plurality of the recess. The contact members include contact tips adapted to electrically couple with the contacts on the integrated circuit device. An electrical interface including at least one circuit trace electrically couples the contact member to metalized pads located along a second surface of the substrate at a location offset from a corresponding contact member. A solder ball is attached to a plurality of the metalized pads.

Abstract: A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures.