Abstract: An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.

Abstract: A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.

Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.

Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.

Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

Abstract: A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.

Abstract: An array of composite polymer-metal contact members adapted to form solder free electrical connections with a first circuit member. The contact members include a resilient polymeric base layer and an array of metalized traces printed on selected portions of the base layer. Conductive plating is applied to the metalized layer to create an array of conductive paths. The resilient polymeric base layer, the metalized layer, and the conductive plating have an aggregate spring constant sufficient to maintain distal portions of the contact members in a cantilevered configuration and to form a stable electrical connection between the distal portions and the first circuit member solely by compressive engagement.

Abstract: A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.

Abstract: An interconnect assembly including a resilient material with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete, free-flowing conductive particles is located in the through holes. The conductive particles are preferably substantially free of non-conductive materials. A plurality of first contact tips are located in the through holes adjacent the first surface and a plurality of second contact tips are located in the through holes adjacent the second surface. The resilient material provides the required resilience, while the conductive particles provide a conductive path substantially free of non-conductive materials.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of contact members are positioned in a plurality of the through openings. The contact members include a base portion and one or more beams. A layer is molded to the housing and the contact members to retain the contact members in the openings. A solder member is preferably coupled with an engagement feature on the base portion of the contact member.

Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.

Abstract: A normally closed connector apparatus for electrically connecting first and second circuit members. An electrically insulative connector housing having a first portion translatable relative to a second portion is provided. The connector housing is adapted to be positioned substantially between the first and second circuit members. A plurality of resilient contact members are retained in the first portion of the housing. The contact members have first distal ends that do not extend substantially above an upper surface of the second portion. Displacement of the second portion relative to the first portion in a translated configuration positions the first distal ends of the contact members above the upper surface of the second portion to electrically couple with the first circuit member.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of contact members are positioned in a plurality of the through openings. The contact members include a base portion, a first beam having a proximal end attached to the base portion and a distal end extending away from the base portion in a first direction, and a second beam having a proximal end attached to the base portion and a distal end extending away from the base portion generally in the first direction. The first and second beams are configured to form at least one loop. At least one tab is attached to the base portion. The tab includes at least one engagement feature mechanically coupled to a solder member.

Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.

Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of electrical contact member are positioned in a plurality of the through openings. The contact members have at least one engagement feature forming a snap-fit relationship with the housing. A stabilizing structure on the housing limits deflection of the contact members in at least one direction.

Abstract: An apparatus and method for making a compliant interconnect assembly adapted to electrically couple a first circuit member to a second circuit member. The first dielectric layer has a first major surface and a plurality of through openings. A plurality of electrical traces are positioned against the first major surface of the first dielectric layer. The electric traces include a plurality of conductive compliant members having first distal ends aligned with a plurality of the openings in the first dielectric layer. The first distal ends are adapted to electrically couple with the first circuit member. The second dielectric layer has a first major surface positioned against the electric traces and the first major surface of the first dielectric layer. The second dielectric layer has a plurality of through openings through which the electric traces electrically couple with the second circuit member.

Abstract: A method and apparatus for achieving a very fine pitch interconnect between a flexible circuit member and another circuit member with extremely co-planar electrical contacts that have a large range of compliance. An electrical interconnect assembly that can be used as a die-level test probe, a wafer probe, and a printed circuit probe is also disclosed. The second circuit member can be a printed circuit board, another flexible circuit, a bare-die device, an integrated circuit device, an organic or inorganic substrate, a rigid circuit and virtually any other type of electrical component. A plurality of electrical contacts are arranged in a housing. The electrical contacts may be arranged randomly or in a one or two-dimensional array. The housing acts as a receptacle to individually locate and generally align the electrical contacts, while preventing adjacent contacts from touching. The first ends of the electrical contacts are electrically coupled to a flexible circuit member.