Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method includes receiving in conjunction with data to be written at a non-volatile memory device an indication from a host that is descriptive of a write-back requirement for the data; and storing the data in a cache memory of the non-volatile memory device and selectively, depending on the indication, controlling whether the data is or is not written back from the cache memory to a non-volatile memory array that comprises a part of the non-volatile memory device.

Abstract: The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.

Abstract: The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method, mobile device, system, and software are devised in order to implement a write method that includes two different types of write commands, depending upon the length of a data burst to memory. A first write command is provided for a first type of burst and/or a second write command is provided for a second type of burst. The first type of burst is a burst of substantially a certain length. The second type of burst has length that is substantially an integer multiple of the length of the first type of burst, such as two or four times the length of the first type of burst.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: A method, apparatus, system, and software product are presented for stopping a continuous burst, or a maximum supported burst, that is used to read from or write to a memory. An indication is provided to release a data bus. Subsequently, the data bus is released in response to the indication, but only after a lapse of time that substantially eliminates unneeded data cycles.

Abstract: A circuit has a first memory, which may be a flash memory or a mass memory, and a random access memory RAM that is distinct from the first memory. A central processing unit CPU couples the first memory to the RAM. Means for encrypting and decrypting in the circuit couples the first memory to the RAM, and is for encrypting and decrypting data between the first memory and the RAM autonomously of the CPU. Preferably, a microprocessor is the means for encrypting and decrypting, and operates to also autonomously read and write to and from, as well as erase from, the RAM. The CPU may be coupled to the first memory and the RAM directly or only through the means for encrypting and decrypting. A device, method, and computer program product are also detailed.

Abstract: A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: The invention relates in general to a method for accessing data stored in a dynamic random access memory. To enable flexible use of different types of memory modules, the invention provides addressing data through at least one address bus, controlling at least data flow to and from the dynamic random access memory through at least one control bus, transferring data to and from the dynamic random access memory through at least one data bus, and clocking the dynamic random access memory through at least one clock input, wherein transferring data to and from the dynamic random access memory through the data bus is operated at a variable data flow rate such that the number of data bits transferred on the data bus within one clock cycle is adjustable through at least one command on the control bus.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: A memory circuit (1) comprises at least a non-volatile random access memory (3) and a random access memory (4). The memory circuit (1) also comprises a memory controller (5) connected by a first bus (6) to the non-volatile random access memory (3) and by a second bus (10) to the random access memory (4). Thus, data can be transmitted between non-volatile random access memory (3) and random access memory (4) via the memory controller (5). The memory circuit comprises a control bus (12) connected to the memory controller (5) to control operation of the memory circuit (1). The invention also relates to a corresponding system and corresponding electronic device (2) in which the memory circuit (1) is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory (3) and a random access memory (4) are used.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: The invention relates to a method for obtaining temperature values from at least two thermal sensors arranged on resources within a three-dimensional die structure determining at least a partial three-dimensional temperature distribution for said die structure and controlling activity of said resources of said dies in response to said three-dimensional temperature distribution.