Abstract: The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Abstract: A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Abstract: The present invention describes a novel methodology for a direct communication between a memory module and a processor of an electronic device (e.g., a mobile phone) using a fast non-volatile random access memory (NVRAM) provided in that memory module. New NVRAM technologies make it possible to have a single memory unit supporting a baseband operation of the electronic device such as the mobile phone. This is possible because NVRAMs are non-volatile (no need for a separate NOR) and fast (equivalent to a DRAM speed). This invention defines ways to connect the fast NVRAM to a baseband communication line through an existing mobile double data rate (DDR) interface. The invention also demonstrates flexibility and extended capabilities of the NVRAM approach by using the NVRAMs in combination with additional optional components such as a mass memory, a dynamic random access memory (DRAM) and an application-specific integration circuit.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: A memory circuit (1) comprises at least a non-volatile random access memory (3) and a random access memory (4). The memory circuit (1) also comprises a memory controller (5) connected by a first bus (6) to the non-volatile random access memory (3) and by a second bus (10) to the random access memory (4). Thus, data can be transmitted between non-volatile random access memory (3) and random access memory (4) via the memory controller (5). The memory circuit comprises a control bus (12) connected to the memory controller (5) to control operation of the memory circuit (1). The invention also relates to a corresponding system and corresponding electronic device (2) in which the memory circuit (1) is used. The invention also relates to a corresponding method in connection with a memory circuit, in which at least a non-volatile random access memory (3) and a random access memory (4) are used.