Patents by Inventor Jason A. Mix

Jason A. Mix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7334325
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Patent number: 7282647
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Patent number: 7040934
    Abstract: In one embodiment of the invention, the apparatus includes a socket connector to connect to a backplane to receive an electronic device. The socket connector includes a plurality of pairs of signal contacts to receive signals from the electronic device, and a plurality of ground frames to ground the electronic device. The ground frames are to connect to a ground plane of the electronic device. The socket connector also includes a set of one or more ground pins to connect to the ground plane, wherein each one of the set is between each of the pairs of signal contacts.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Yun Ling, Jason A. Mix
  • Publication number: 20050082088
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Application
    Filed: November 16, 2004
    Publication date: April 21, 2005
    Inventors: Weston Roth, Jayne Mershon, Xang Moua, Jason Mix
  • Publication number: 20040121655
    Abstract: In one embodiment of the invention, the apparatus includes a socket connector to connect to a backplane to receive an electronic device. The socket connector includes a plurality of pairs of signal contacts to receive signals from the electronic device, and a plurality of ground frames to ground the electronic device. The ground frames are to connect to a ground plane of the electronic device. The socket connector also includes a set of one or more ground pins to connect to the ground plane, wherein each one of the set is between each of the pairs of signal contacts.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Yun Ling, Jason A. Mix
  • Publication number: 20040118597
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Patent number: 6710266
    Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Jason A. Mix, Yun Ling, Alok Tripathi, Kent E. Mallory
  • Publication number: 20040016569
    Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 29, 2004
    Inventors: Jason A. Mix, Yun Ling, Alok Tripathi, Kent E. Mallory
  • Publication number: 20030063677
    Abstract: A method and apparatus for the multi-level coding for communication for computer bus data transfers are described. An input signal and delayed versions of the input are combined to create an encoded output signal. An input signal and delayed versions of the output are combined to create a decoded output signal.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Applicant: Intel Corporation
    Inventors: Jason A. Mix, Michael W. Leddige, Howard L. Heck