Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation, wherein the write operation includes transmitting a number of write transactions received from a host along with a number of spurious transactions to a memory, and wherein the number of spurious transactions are transmitted at a particular rate among the number of received write transactions.

Abstract: Converting data signals includes determining whether a coupled interface converter paddle coupled to a serdes is a first interface converter paddle or a second interface converter paddle. The first interface converter paddle is associated with a first communication protocol, and the second interface converter paddle is associated with a second communication protocol. The communication protocol associated with the coupled interface converter paddle is identified. Data signals are received from the coupled interface converter paddle, and deserialized according to the identified communication protocol.

Abstract: A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer.

Abstract: One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.

Abstract: One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of circuit characteristics for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: The present invention is a technique to minimize crosstalk in multilayer IC packages. According to one or more embodiments of the present invention, signal routing layers are separated by planes for power and ground. Signal trace routing on the routing layers follows either horizontal, vertical or diagonal directions for obtaining high routing densities in the package as is the present design practice. The power and ground planes in one embodiment of the present invention are constructed as a mesh having groups of colinear perforations. The groups are oriented at an arbitrary angle that is chosen to minimize the crossings of groups of signals over mesh openings. It is guaranteed that the number of mesh openings that any given set of three traces encounters is reduced by at least a factor of two. Thus the present invention reduces crosstalk in the package by approximately 50%.

Abstract: A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer.

Abstract: A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip semiconductor device includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry, a first power supply wiring and a first ground wiring disposed in the semiconductor substrate, a signal wiring disposed in the semiconductor substrate, and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns. Bumps in predetermined locations in the matrix are selectively coupled to the first power supply wiring and the first ground wiring.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: A circuit arrangement for interconnecting electronic components such as integrated circuit devices, chip packages and/or circuit boards includes signal, first fixed potential (e.g., power) and second fixed potential (e.g., ground) interconnects arranged into an interconnection layout pattern that offers greater flexibility, performance and cost effectiveness than conventional patterns. In some implementations, the interconnection layout pattern incorporates one or more tiles of interconnects, with each tile defining a plurality of interconnect positions arranged into at least three rows and at least four columns. For each tile, a signal interconnect is disposed at each of the three interconnect positions in each of the first and fourth columns, and one each of a signal interconnect, a first fixed potential interconnect and a second fixed potential interconnect are disposed in each of the second and third columns.

Abstract: The present invention includes a micro-electromechanical system and voltage shifter, method of synchronizing an electronic system and a micromechanical system of a micro-electromechanical system. According to one aspect, the present invention provides a micro-electromechanical system voltage shifter including at least one node; a capacitor including plural opposing conductive plates; a micromechanical system configured to vary the capacitance of the capacitor; an electrical system configured to selectively couple the capacitor and the at least one node; and a mixer configured to output a product signal to synchronize the micromechanical system and the electrical system.

Abstract: Disclosed is a redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device and a method for making the same. The redistribution layer includes a plurality of slot pads arranged along a periphery of the redistribution layer. The plurality of slot pads are formed from the patterned metallization layer. An array of bump pads are arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads are formed from the patterned metallization layer. The redistribution layer further includes a plurality of traces that are formed from the patterned metallization layer and are configured to interconnect the plurality of slot pads to the array of bump pads. Each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces.