Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: A plasma processing apparatus may include a support configured to receive a substrate, a gas distribution plate (GDP) including a plurality of nozzles facing the support, a main splitter configured to supply a process gas, and an additional splitter configured to supply an acceleration gas or a deceleration gas. The plurality of nozzles may include a plurality of central nozzles, a plurality of outer nozzles, a plurality of middle nozzles configured to spray the process gas and the acceleration gas, a plurality of first nozzles, and a plurality of second nozzles.

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.

Abstract: A system for fabricating a semiconductor device may include a chamber, an electrostatic chuck used to load a substrate, a power source supplying an RF power to the electrostatic chuck, an impedance matcher between the power source and the electrostatic chuck, and a power transmission unit connecting the electrostatic chuck to the impedance matcher. The power transmission unit may include a power rod, which is connected to the electrostatic chuck and has a first outer diameter, and a coaxial cable. The coaxial cable may include an inner wire, an outer wire, and a dielectric material between the outer and inner wires. The inner wire connects the power rod to the impedance matcher and has a second outer diameter less than the first outer diameter. The outer wire is connected to the chamber and is provided to enclose the inner wire and has a first inner diameter less than the first outer diameter and greater than the second outer diameter.

Abstract: A substrate processing apparatus including a process chamber; a susceptor in the process chamber; and an inner edge ring and an outer edge ring on the susceptor, wherein the inner edge ring includes a semiconductor, the outer edge ring includes an insulator, an upper surface of the outer edge ring is at a higher level than an upper surface of the inner edge ring, and the outer edge ring has an overhang extending onto the inner edge ring.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

Abstract: A semiconductor processing apparatus includes a chamber housing, an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer, an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring, and a ring voltage supply configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform comprises a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the negative voltage has a magnitude that increases during the second time period.

Abstract: A plasma processing apparatus may include a support configured to receive a substrate, a gas distribution plate (GDP) including a plurality of nozzles facing the support, a main splitter configured to supply a process gas, and an additional splitter configured to supply an acceleration gas or a deceleration gas. The plurality of nozzles may include a plurality of central nozzles, a plurality of outer nozzles, a plurality of middle nozzles configured to spray the process gas and the acceleration gas, a plurality of first nozzles, and a plurality of second nozzles.

Abstract: A system for fabricating a semiconductor device may include a chamber, an electrostatic chuck used to load a substrate, a power source supplying an RF power to the electrostatic chuck, an impedance matcher between the power source and the electrostatic chuck, and a power transmission unit connecting the electrostatic chuck to the impedance matcher. The power transmission unit may include a power rod, which is connected to the electrostatic chuck and has a first outer diameter, and a coaxial cable. The coaxial cable may include an inner wire, an outer wire, and a dielectric material between the outer and inner wires. The inner wire connects the power rod to the impedance matcher and has a second outer diameter less than the first outer diameter. The outer wire is connected to the chamber and is provided to enclose the inner wire and has a first inner diameter less than the first outer diameter and greater than the second outer diameter.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.